Intel 80C186XL, 80C188XL user manual Suspension of DMA Transfers, Initializing the DMA Unit

DIRECT MEMORY ACCESS UNIT

10.2.2 Suspension of DMA Transfers

Whenever the CPU receives an NMI, all DMA activity is suspended at the end of the current transfer. The CPU suspends DMA activity by setting the DHLT bit in the Interrupt Status Regis- ter (Figure 8-14 on page 8-23). When an IRET instruction is executed, the CPU clears the DHLT bit and DMA transfers are allowed to resume. Software can read and write the DHLT bit.

NOTE

Do not write to the DHLT bit while Timer/Counter Unit interrupts are enabled. A conflict with the internal use of the register may cause incorrect processing of timer interrupts.

The DHLT bit does not function when the interrupt controller is in slave mode.

10.2.3 Initializing the DMA Unit

Use the following sequence when programming the DMA Unit:

1.Program the source and destination pointers for all used channels.

2.Program the DMA Control Registers in order of highest-priority channel to lowest- priority channel.

10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT

This section covers hardware interfacing and performance factors for the DMA Unit.

10.3.1 DRQ Pin Timing Requirements

The DRQ pins are sampled on the falling edge of CLKOUT. The DRQ pins must be set up a min-

imum of TINVCL before CLKOUT falling, to guarantee recognition at a specific clock edge. Refer to the data sheet for specific values.

The DRQ pins have an internal synchronizer. Violating the setup time can cause only a missed DMA request, not a processor malfunction.

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