BUS INTERFACE UNIT

Most memory and peripheral devices latch data on the rising edge of the write strobe. Address, chip-select and data must be valid (set up) prior to the rising edge of WR. TAW, TCW and TDW de- fine the minimum data setup requirements. The value calculated by their respective equations must be greater than the device requirements. To increase the calculated value, insert wait states.

LA15:1

RD

LA0

WR

BHE

A0:14

OE

I/O1:8

WE

CS1

A0:14

OE

I/O1:8

WE

AD7:0

AD15:8

LCS

CS1

A1106-0A

Figure 3-22. 16-Bit Bus Read/Write Device Interface

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Intel 80C186XL, 80C188XL user manual LA151, LA0 BHE, A014 O18 CS1 AD70 AD158, Lcs