Intel 80C186XL Instruction Set Descriptions, Table C-4.Instruction Set Continued, Name, Operation

Models: 80C186XL 80C188XL

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ADD dest, src

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)

Name

Description

Operation

Flags

Affected

 

 

 

 

 

 

 

ADD

Addition:

(dest) (dest) + (src)

AF

 

ADD dest, src

 

CF

 

 

DF –

 

Sums two operands, which may be

 

 

 

IF –

 

bytes or words, replaces the

 

 

 

OF

 

destination operand. Both operands

 

 

 

PF

 

may be signed or unsigned binary

 

 

 

SF

 

numbers (see AAA and DAA).

 

 

 

TF –

 

Instruction Operands:

 

 

 

ZF ¸

 

ADD reg, reg

 

 

 

ADD reg, mem

 

 

 

ADD mem, reg

 

 

 

ADD reg, immed

 

 

 

ADD mem, immed

 

 

 

ADD accum, immed

 

 

 

 

 

 

AND

And Logical:

(dest) (dest) and (src)

AF ?

 

AND dest, src

(CF) 0

CF

 

(OF) 0

DF –

 

Performs the logical "and" of the two

 

 

IF –

 

operands (byte or word) and returns

 

 

 

OF

 

the result to the destination operand. A

 

 

 

PF

 

bit in the result is set if both corre-

 

 

 

SF

 

sponding bits of the original operands

 

 

 

TF –

 

are set; otherwise the bit is cleared.

 

 

 

ZF ¸

 

Instruction Operands:

 

 

 

AND reg, reg

 

 

 

AND reg, mem

 

 

 

AND mem, reg

 

 

 

AND reg, immed

 

 

 

AND mem, immed

 

 

 

AND accum, immed

 

 

 

 

 

 

NOTE: The three symbols used in the Flags Affected column are defined as follows:

the contents of the flag remain unchanged after the instruction is executed ¸? the contents of the flag is undefined after the instruction is executed

the flag is updated after the instruction is executed

C-6

Page 329
Image 329
Intel 80C186XL Instruction Set Descriptions, Table C-4.Instruction Set Continued, Name, Operation, Flags, Affected