Intel 80C188XL Contents, Chapter, Once Mode, Appendix A, Appendix B, Input Synchronization

		CONTENTS
11.3.1.4	Transcendental Instructions	11-5
11.3.1.5	Constant Instructions	11-6
11.3.1.6	Processor Control Instructions	11-6

11.3.2		80C187 Data Types	11-7
11.4 MICROPROCESSOR AND COPROCESSOR OPERATION			11-7
11.4.1		Clocking the 80C187	11-10
11.4.2 Processor Bus Cycles Accessing the 80C187			11-10
11.4.3		System Design Tips	11-11
11.4.4		Exception Trapping	11-13
11.5 EXAMPLE MATH COPROCESSOR ROUTINES			11-13
CHAPTER 12
ONCE MODE
12.1	ENTERING/LEAVING ONCE MODE		12-1
APPENDIX A
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
A.1 80C186 INSTRUCTION SET ADDITIONS			A-1
A.1.1		Data Transfer Instructions	A-1
A.1.2		String Instructions	A-2
A.1.3		High-Level Instructions	A-2
A.2 80C186 INSTRUCTION SET ENHANCEMENTS			A-8
A.2.1		Data Transfer Instructions	A-8
A.2.2		Arithmetic Instructions	A-9
A.2.3		Bit Manipulation Instructions	A-9
A.2.3.1		Shift Instructions	A-9
A.2.3.2		Rotate Instructions	A-10
APPENDIX B
INPUT SYNCHRONIZATION
B.1 WHY SYNCHRONIZERS ARE REQUIRED			B-1
B.2	ASYNCHRONOUS PINS		B-2

APPENDIX C

INSTRUCTION SET DESCRIPTIONS

APPENDIX D

INSTRUCTION SET OPCODES AND CLOCK CYCLES

INDEX

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