Intel 80C188XL, 80C186XL Interrupt Acknowledge Bus Cycle, Write Cycle Critical Timing Parameters

BUS INTERFACE UNIT

The minimum device data hold time (from WR high) is defined by TDH. The calculated value must be greater than the minimum device requirements; however, the value can be changed only by decreasing the clock rate.

Table 3-5. Write Cycle Critical Timing Parameters

Memory Device			Description							Equation
Parameter
TWC	Write cycle time									4TCLCL
TAW	Address valid to end of write strobe								high)	3TCLCL – TADLTCH
								(WR
TCW	Chip enable		to end of write strobe (WR high)							3TCLCL
		(LCS)
TWR	Write recover time									TWHLH
TDW	Data valid to write strobe					high)				2TCLCL
				(WR
TDH	Data hold from write strobe						high)			TWHDX
					(WR
TWP	Write pulse width									TWLWH

TWC and TWP define the minimum time (maximum frequency) a device can process write bus cy- cles. TWR determines the minimum time from the end of the current write cycle to the start of the next write cycle. All three parameters require that calculated values be greater than device re- quirements. The calculated TWC and TWP values increase with the insertion of wait states. The cal- culated TWR value, however, can be changed only by decreasing the clock rate.

3.5.3Interrupt Acknowledge Bus Cycle

Interrupt expansion is accomplished by interfacing the Interrupt Control Unit with a peripheral device such as the 82C59A Programmable Interrupt Controller. (See Chapter 8, “Interrupt Con- trol Unit,” for more information.) The BIU controls the bus cycles required to fetch vector infor- mation from the peripheral device, then passes the information to the CPU. These bus cycles, collectively known as Interrupt Acknowledge bus cycles, operate similarly to read bus cycles. However, instead of generating RD to enable the peripheral, the INTA signal is used. Figure 3-23 illustrates a typical Interrupt Acknowledge (or INTA) bus cycle.

An Interrupt Acknowledge bus cycle consists of two consecutive bus cycles. LOCK is generated to indicate the sequential bus operation. The second bus cycle strobes vector information only from the lower half of the bus (D7:0). In a 16-bit bus system, the upper half of the bus (D15:8) floats.

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