Intel 80C188XL, 80C186XL user manual Timer 2 Control Register, T2CON, Defines Timer 2 operation

TIMER/COUNTER UNIT

Register Name:

Register Mnemonic:

Register Function:

15

E	I	I
N	N	N
	H	T

Timer 2 Control Register

T2CON

Defines Timer 2 operation.

M

C

0

C

O

N

T

A1298-0A

Bit	Bit Name	Reset			Function
Mnemonic		State
EN	Enable	0	Set to enable the timer. This bit can be written
			only when the	INH	bit is set.
INH	Inhibit	X	Set to enable writes to the EN bit. Clear to
			ignore writes to the EN bit. The			INH	bit is not
			stored; it always reads as zero.
INT	Interrupt	X	Set to generate an interrupt request when the
			Count register equals a Maximum Count
			register. Clear to disable interrupt requests.
MC	Maximum	X	This bit is set when the counter reaches a
	Count		maximum count. The MC bit must be cleared
			by writing to the Timer Control register. This
			is not done automatically. If MC is clear, the
			counter has not reached a maximum count.
CONT	Continuous	X	Set to cause the timer to run continuously.
	Mode		Clear to disable the counter (clear the EN bit)
			after each counting sequence.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 9-6. Timer 2 Control Register

9-9