Intel 80C188XL, 80C186XL See also Bus cycles, See also Refresh Control Unit, Index-3

									INDEX
Data sheets, obtaining from BBS, 1-5							synchronization
Data transfers,		3-1–3-6					destination-synchronized, 10-5
instructions, 2-18							selecting, 10-18
PCB considerations,						4-5	source-synchronized, 10-5
PSW flag storage formats, 2-19							unsynchronized, 10-6
See also Bus cycles							timed DMA transfer example, 10-22–10-27
Data types,	2-37–2-38						transfers, 10-1–10-27
DI register,	2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32,						count, 10-7
2-34								programming, 10-18–10-19
Digital one-shot, code example, 9-17–9-23							direction, 10-3
Direct Memory Access (DMA) Unit, 10-1–10-27							rates, 10-21
and BIU,		10-8					size, 10-3
and CSU,		10-8						selecting, 10-14
and PCB, 10-3							suspending,		10-7, 10-20
arming channel,					10-18		terminating,		10-7
DMA acknowledge signal, 10-2, 10-22							Direction Flag (DF), 2-7, 2-9, 2-23
DRQ timing, 10-20							Display, defined, A-2
examples, 10-22–10-27							Divide Error trap (Type 0 exception), 2-43
HALT bit, 8-22, 8-23, 10-20							DMA Control Register (DxCON), 10-15
hardware considerations, 10-20–10-22							DMA Destination Pointer Register, 10-13, 10-14
initialization code, 10-22–10-27							DMA Source Pointer Register, 10-11, 10-12
initializing,			10-20				Documents, related, 1-3
interrupts,			10-8				DRAM controllers
generating on terminal count, 10-19							and wait state control, 7-5
introduction,				10-1			clocked, 7-5
latency, 10-21							design guidelines,		7-5
modules, 10-8–10-9							unclocked, 7-5
overview, 10-1–10-10							See also Refresh Control Unit
pointers, programming, 10-10–10-14							DS register,	2-1, 2-5, 2-6, 2-13, 2-30, 2-34, 2-43
priority							DX register,	2-1, 2-5, 2-36, 3-6
channel,				10-8–10-9, 10-19			E
fixed, 10-8–10-10
rotating,				10-10			Effective Address (EA), 2-13
programming, 10-17–10-20
							calculation, 2-28
arming channel,						10-18
							Emulation mode, 11-1
channel priority,						10-19
							End-of-Interrupt (EOI)
initializing,					10-20
							command, 8-21
interrupts,					10-19
							register, 8-21, 8-22, 8-27, 8-28
suspending transfers, 10-20
							ENTER instruction, A-2
synchronization,						10-18
							ES register,	2-1, 2-5, 2-6, 2-13, 2-30, 2-34
transfer count, 10-18–10-19
							Escape opcode fault (Type 7 exception), 2-44, 10-2
programming, pointers, 10-10–10-14
							Exceptions,	2-43–2-44
requests,		10-3
							priority, 2-46–2-49
external,				10-4
							Execution Unit (EU), 2-1, 2-2
internal,				10-6
							Extra segment, 2-5
		software, 10-6
		Timer 2, 10-6
selecting source,						10-17

Index-3