80C186XL/80C188XL Microprocessor User’s Manual
80C186XL/80C188XL Microprocessor User’s Manual
1995
Intel Corporation Literature Sales P.O. Box
CONTENTS
CHAPTER
INTRODUCTION
CHAPTER
CONTENTS
CHAPTER
BUS INTERFACE UNIT
CONTENTS
CLOCK GENERATION AND POWER MANAGEMENT
CHAPTER
PERIPHERAL CONTROL BLOCK
CONTENTS
CHAPTER
REFRESH CONTROL UNIT
CHAPTER
CONTENTS
TIMER/COUNTER UNIT
DIRECT MEMORY ACCESS UNIT
CHAPTER
CONTENTS
CHAPTER
MATH COPROCESSING
CONTENTS
ONCE MODE
CHAPTER
APPENDIX A
FIGURES
CONTENTS
Figure
Page
CONTENTS
FIGURES
Figure
Page
CONTENTS
FIGURES
Figure
Page
CONTENTS
FIGURES
Figure
Page
TABLES
CONTENTS
Table
Page
CONTENTS
TABLES
Table
Page
EXAMPLES
CONTENTS
Example
Page
Introduction
Page
CHAPTER INTRODUCTION
1.1HOW TO USE THIS MANUAL
INTRODUCTION
1.2RELATED DOCUMENTS
INTRODUCTION
Table 1-2.Related Documents and Software
1.3.1FaxBack Service
1.3ELECTRONIC SUPPORT SYSTEMS
1.3.2Bulletin Board System BBS
1.3.3CompuServe Forums
1.3.4World Wide Web
1.4TECHNICAL SUPPORT
1.5PRODUCT LITERATURE
1.6TRAINING CLASSES
Page
Overview of the 80C186 Family Architecture
Page
CHAPTER OVERVIEW OF THE 80C186 FAMILY
ARCHITECTURE
2.1ARCHITECTURAL OVERVIEW
2.1.1Execution Unit
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.1.2Bus Interface Unit
2.1.3General Registers
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Figure 2-3.General Registers
2.1.4Segment Registers
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Table 2-1.Implicit Use of General Registers
2.1.5Instruction Pointer
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Figure 2-4.Segment Registers
2.1.6Flags
2.1.7Memory Segmentation
Register Name
Register Mnemonic
Register Function
Reset
2.1.8Logical Addresses
Data: DS Code: CS Stack: SS Extra: ES
B E H J
FFFFFH A B D E G J K 0H
C F H I
Physical Address Offset 3H Segment Base Logical
Addresses Segment Base
Offset 13H
2C4H 2C3H 2C2H 2C1H 2C0H 2BFH 2BEH 2BDH 2BCH 2BBH
2.1.9Dynamically Relocatable Code
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Table 2-2.Logical Address Sources
Before
2.1.10 Stack Implementation
2.1.11 Reserved Memory and I/O Space
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Figure 2-10.Stack Operation
2.2SOFTWARE OVERVIEW
2.2.1Instruction Set
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.1Data Transfer Instructions
Table 2-3.Data Transfer Instructions
General-Purpose
I = Interrupt Enable Flag T = Trap Flag
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Figure 2-11.Flag Storage Format
2.2.1.2Arithmetic Instructions
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Table 2-4.Arithmetic Instructions
Addition
Subtraction
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.3Bit Manipulation Instructions
Table 2-6.Bit Manipulation Instructions
Bit Pattern
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.4String Instructions
Table 2-7.String Instructions
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.5Program Transfer Instructions
SI DI CX AL/AX DF ZF
Scan value Destination for LODS Source for STOS
Unconditional transfer instructions can transfer control either to a target instruction within the current code segment intrasegment transfer or to a different code segment intersegment trans- fer. The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans- fer FAR. The transfer is made unconditionally when the instruction is executed. CALL, RET and JMP are all unconditional transfers
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Table 2-9.Program Transfer Instructions
Conditional Transfers
Unconditional Transfers
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Mnemonic
Condition Tested
“Jump if…”
2.2.2Addressing Modes
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.6Processor Control Instructions
Table 2-11.Processor Control Instructions
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.2.2Memory Addressing Modes
Encoded in the Instruction Explicit in the
Displacement
Opcode
Mod R/M
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Displacement
Opcode
Mod R/M
BX or BP
Displacement
Opcode
Displacement
Opcode
Mod R/M
BX or BP
High Address
Opcode SI DI
Source EA Destination EA
Opcode Data
Port Address Direct Port Addressing
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Table 2-12.Supported Data Types
Type
Description
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
NMI CPU
Maskable Interrupt Request Interrupt Acknowledge
Interrupt Control Unit
External Interrupt Sources
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Figure 2-25.Interrupt Vector Table
3.The current CS and IP are pushed onto the stack
Stack PSW
Divide Error — Type
Single Step — Type
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.3.1.2Maskable Interrupts
Numerics Coprocessor Fault — Type
Breakpoint Interrupt — Type
Interrupt on Overflow — Type
Array Bounds Check — Type
2.3.2Software Interrupts
2.3.3Interrupt Latency
2.3.4Interrupt Response Time
Clocks
Total
2.3.5Interrupt and Exception Priority
Divide Error
Push PSW, CS, IP Fetch Divide Error Vector
Service Routine IRET Execute Divide
Service Routine IRET
Push PSW, CS, IP Fetch Divide Error Vector
Service Routine IRET Trap Flag = ???
NMI Instruction
Trap Flag =
Interrupt Enable Bit IE = Trap Flag TF =
Page
Bus Interface Unit
Page
CHAPTER BUS INTERFACE UNIT
3.1MULTIPLEXED ADDRESS AND DATA BUS
3.2ADDRESS AND DATA BUS CONCEPTS
3.2.116-BitData Bus
1 MByte
512 KBytes
512 KBytes
Even Byte Transfer
Odd Byte Transfer
A19:1
D15:8 BHE
D7:0 A0 Low
BUS INTERFACE UNIT
First Bus Cycle
Second Bus Cycle
3.2.28-BitData Bus
A19:0
D7:0
3.3MEMORY AND I/O INTERFACES
First Bus Cycle
3.3.116-BitBus Memory and I/O Requirements
3.3.28-BitBus Memory and I/O Requirements
3.4BUS CYCLE OPERATION
Phase
CLKOUT
Falling
Rising
Bus Ready
3.4.1Address/Status Phase
or TI
Signals From CPU
3.4.2Data Phase
3.4.3Wait States
or TW
T1 T2 T3 TW TW T4 CLKOUT
CS1 CS2 CS3 CS4 ALE CLKOUT
Wait State Module Input Input
Clear Clock
READY
Wait State Module CS1 Enable CS2
Load
READY
CLKOUT
3.4.4Idle States
CLKOUT
ARDY SRDY
•The instruction prefetch queue is full
3.5BUS CYCLES
3.5.1Read Bus Cycles
BUS INTERFACE UNIT
Table 3-2. Read Bus Cycle Types
CLKOUT
27C256
3.5.2Write Bus Cycles
27C256
CLKOUT
LA15:1 RD LA0 WR BHE
A0:14 OE I/O1:8 WE CS1 A0:14 OE I/O1:8 WE
AD7:0 AD15:8
BUS INTERFACE UNIT
3.5.3Interrupt Acknowledge Bus Cycle
BUS INTERFACE UNIT
Table 3-5.Write Cycle Critical Timing Parameters
CLKOUT ALE S2:0 INTA0 INTA1 AD15:0 AD7:0 LOCK
DT/R DEN A19:16 A15:8 BHE RD, WR
T1 T2
T3 T4
Processor
3.5.4HALT Bus Cycle
CLKOUT
3.5.5Temporarily Exiting the HALT Bus State
CLKOUT HOLD HLDA AD15:0 AD7:0 A15:8 A19:16
CONTROL
CLKOUT ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHE
RFSH
BUS INTERFACE UNIT
3.5.6Exiting HALT
3.6SYSTEM DESIGN ALTERNATIVES
CLKOUT
NMI/INTx ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHE
RFSH
3.6.1Buffering the Data Bus
A19:16
3.6.2Synchronizing Software and Hardware Events
3.6.3Using a Locked Bus
3.6.4Using the Queue Status Signals
Table 3-7.Queue Status Signal Decoding
BUS INTERFACE UNIT
3.7MULTI-MASTERBUS SYSTEM DESIGNS
3.7.1Entering Bus HOLD
BUS INTERFACE UNIT
Figure 3-33.Queue Status Timing
CLKOUT
BUS INTERFACE UNIT
3.7.1.2Refresh Operation During a Bus HOLD
CLKOUT
3.7.2Exiting HOLD
+5 HLDA RESET HOLD
PRE DQ CLR
Latched HLDA
3.8BUS CYCLE PRIORITIES
9.DMA bus cycles
Page
Peripheral Control Block
Page
CHAPTER PERIPHERAL CONTROL BLOCK
4.1PERIPHERAL CONTROL REGISTERS
4.2PCB RELOCATION REGISTER
PCB Relocation Register
RELREG
Relocates the PCB within memory or I/O space
Register Name
PERIPHERAL CONTROL BLOCK
Table 4-1.Peripheral Control Block
Function
Function
4.4ACCESSING THE PERIPHERAL CONTROL BLOCK
4.4.2READY Signals and Wait States
4.3RESERVED LOCATIONS
4.4.1Bus Cycles
4.4.3F-BusOperation
Word reads
address
Byte reads
4.5SETTING THE PCB BASE LOCATION
4.4.3.2Accessing the Peripheral Control Registers
4.4.3.3Accessing Reserved Locations
PERIPHERAL CONTROL BLOCK
Page
Page
Clock Generation and Power Management
Page
CHAPTER CLOCK GENERATION AND POWER MANAGEMENT
5.1CLOCK GENERATION
5.1.1Crystal Oscillator
CLOCK GENERATION AND POWER MANAGEMENT
Z0 = Inverter Output Z
180˚
5.1.1.1Oscillator Operation
Fundamental
CLOCK GENERATION AND POWER MANAGEMENT
Figure 5-4.Equations for Crystal Calculations
CLKOUT
Third-OvertoneCrystal
CLOCK GENERATION AND POWER MANAGEMENT
5.1.1.2Selecting Crystals
5.1.2Using an External Oscillator
5.1.4Reset and Clock Synchronization
5.1.3Output from the Clock Generator
RESET IN 1µf typical
CLOCK GENERATION AND POWER MANAGEMENT
Figure 5-5.Simple RC Circuit for Powerup Reset
50 k typical
CLOCK GENERATION AND POWER MANAGEMENT
RESET
Figure 5-6.Cold Reset Waveform
X1 Vcc
CLOCK GENERATION AND POWER MANAGEMENT
Figure 5-7.Warm Reset Waveform
5.2POWER MANAGEMENT
5.2.1Power-SaveMode
CLOCK GENERATION AND POWER MANAGEMENT
5.2.1.1Entering Power-SaveMode
Register Name Register Mnemonic Register Function
Power Save Register PWRSAV
Enables and sets clock division factor 0 F F 1
CLOCK GENERATION AND POWER MANAGEMENT
CLKOUT WR
CLOCK GENERATION AND POWER MANAGEMENT
Figure 5-10. Power-SaveClock Transition
5.2.1.2Leaving Power-SaveMode
CLOCK GENERATION AND POWER MANAGEMENT
Chip-SelectUnit
Page
6.2CHIP-SELECTUNIT FEATURES AND BENEFITS
CHAPTER CHIP-SELECTUNIT
6.1COMMON METHODS FOR GENERATING CHIP-SELECTS
6.3CHIP-SELECTUNIT FUNCTIONAL OVERVIEW
Chip-SelectsUsing
Chip-SelectsUsing
CHIP-SELECTUNIT
Internal
device EPROM or Flash memory types
1.The chip-selectis enabled
6.4PROGRAMMING
6.4.1Initialization Sequence
Register Name
Register Mnemonic
Register Function
CHIP-SELECTUNIT
Register Name
Register Mnemonic
Register Function
CHIP-SELECTUNIT
Register Name
Register Mnemonic
Register Function
CHIP-SELECTUNIT
Register Name
Register Mnemonic
Register Function
CHIP-SELECTUNIT
MPCS
Register Mnemonic
CHIP-SELECTUNIT
Figure 6-9.MPCS Register Definition
6.4.2Programming the Active Ranges
Table 6.3 LCS Active Range
CHIP-SELECTUNIT 6.4.2.2LCS Active Range
6.4.2.3MCS Active Range
Table 6-4.MCS Active Range
Starting Address
6.4.3Bus Wait State and Ready Control
CHIP-SELECTUNIT 6.4.2.4PCS Active Range
Table 6-6.PCS Active Range
6.4.4Overlapping Chip-Selects
BUS READY R2 Control Bit Wait
Wait State Value R1:0 State Counter
READY Wait State Ready
6.4.5Memory or I/O Bus Cycle Decoding
6.4.6Programming Considerations
6.6.1Example 1: Typical System Configuration
CSU Chip Select Device select
External Master Chip Select
6.5CHIP-SELECTSAND BUS HOLD
CHIP-SELECTUNIT
Figure 6-13.Typical System
CHIP-SELECTUNIT
Example 6-1.Initializing the Chip-SelectUnit
CHIP-SELECTUNIT
CHIP-SELECTUNIT
Place memory variables here
Refresh Control Unit
Page
CHAPTER REFRESH CONTROL UNIT
7.1THE ROLE OF THE REFRESH CONTROL UNIT
7.2REFRESH CONTROL UNIT CAPABILITIES
7.3REFRESH CONTROL UNIT OPERATION
Refresh Control Unit Operation Set E Bit
7.4REFRESH ADDRESSES
REFRESH CONTROL UNIT
Figure 7-3.Refresh Address Formation
7.5REFRESH BUS CYCLES
7.6GUIDELINES FOR DESIGNING DRAM CONTROLLERS
REFRESH CONTROL UNIT
Table 7-1.Identification of Refresh Bus Cycles
T3/TW
7.7PROGRAMMING THE REFRESH CONTROL UNIT
7.7.1Calculating the Refresh Interval
7.7.2Refresh Control Unit Registers
REFRESH CONTROL UNIT
RFBASE
Register Name:Refresh Base Address Register
Register Mnemonic
Refresh Clock Interval Register
RFTIME
Sets refresh rate
Register Name
7.7.3Programming Example
Register Name Register Mnemonic Register Function
Refresh Control Register RFCON
Controls Refresh Unit operation
REFRESH CONTROL UNIT
Example 7-1.Initializing the Refresh Control Unit
7.8REFRESH OPERATION AND BUS HOLD
REFRESH CONTROL UNIT
CLKOUT
Page
Interrupt Control Unit
Page
CHAPTER INTERRUPT CONTROL UNIT
8.1FUNCTIONAL OVERVIEW
8.2MASTER MODE
8.2.1Generic Functions in Master Mode
Table 8-1.Default Interrupt Priorities
INTERRUPT CONTROL UNIT 8.2.1.1Interrupt Masking
8.2.1.2Interrupt Priority
Interrupt Name
INTERRUPT CONTROL UNIT
8.2.1.3Interrupt Nesting
8.3FUNCTIONAL OPERATION IN MASTER MODE
8.3.2Priority Resolution
8.3.1Typical Interrupt Sequence
•the Interrupt Control Unit has been initialized
8.3.3Cascading with External 8259As
INTERRUPT CONTROL UNIT
8.3.2.2Interrupts That Share a Single Source
INT0
8.3.4Interrupt Acknowledge Sequence
8.3.5Polling
INTERRUPT CONTROL UNIT
Table 8-2.Fixed Interrupt Types
8.3.6Edge and Level Triggering
8.3.7Additional Latency and Response Time
8.4PROGRAMMING THE INTERRUPT CONTROL UNIT
8.4.1Interrupt Control Registers
INTERRUPT CONTROL UNIT
Register Mnemonic: TCUCON, DMA0CON, DMA1CON
I2CON, I3CON
Register Mnemonic
I0CON, I1CON
Register Mnemonic
INTERRUPT CONTROL UNIT
8.4.2Interrupt Request Register
Interrupt Request Register
REQST
Stores pending interrupt requests
Interrupt Mask Register
IMASK
Masks individual interrupt sources
8.4.4Priority Mask Register
8.4.5In-ServiceRegister
Register Name
Priority Mask Register
Register Mnemonic
8.4.6Poll and Poll Status Registers
Figure 8-10. In-ServiceRegister
Register Name
Register Mnemonic
Register Name Register Mnemonic Register Function
Poll Register POLL
INTERRUPT CONTROL UNIT
Figure 8-11.Poll Register
8.4.7End-of-InterruptEOI Register
Read to check for pending interrupts when polling
Register Name Register Mnemonic Register Function
Poll Status Register POLLSTS
8.4.8Interrupt Status Register
Used to issue an EOI command
Register Name Register Mnemonic Register Function
End-of-InterruptRegister EOI
8.5SLAVE MODE
Register Name Register Mnemonic Register Function
Interrupt Status Register INTSTS
Figure 8-15.Interrupt Control Unit in Slave Mode
INT0 INTA 80186 Modular Core Select IRQ
8259A
82C59A
8.5.1Slave Mode Programming
Table 8-5.Slave Mode Fixed Interrupt Type Bits
INTERRUPT CONTROL UNIT
8.5.1.1Interrupt Vector Register
INTVEC
Register Mnemonic
INTERRUPT CONTROL UNIT
8.5.1.2End-Of-InterruptRegister
End-of-InterruptRegister in Slave Mode
Used to issue the EOI command
Register Name
Register Mnemonic
8.5.2Interrupt Vectoring in Slave Mode
Interrupt presented to Interrupt Control Unit
INTERRUPT CONTROL UNIT
Page
Timer/Counter Unit
Page
CHAPTER TIMER/COUNTER UNIT
9.1FUNCTIONAL OVERVIEW
T0 In
TIMER/COUNTER UNIT
T0IN
T1IN T0OUT T1OUT
TIMER/COUNTER UNIT
Figure 9-3.Timers 0 and 1 Flow Chart
TIMER/COUNTER UNIT
Figure 9-3.Timers 0 and 1 Flow Chart Continued
9.2PROGRAMMING THE TIMER/COUNTER UNIT
Dual Maximum Count Mode
Single Maximum Count Mode
Maxcount A
Timer 0 and 1 Control Registers T0CON, T1CON
Defines Timer 0 and 1 operation
TIMER/COUNTER UNIT
Figure 9-5.Timer 0 and Timer 1 Control Registers
TIMER/COUNTER UNIT
Register Name Register Mnemonic Register Function
Timer 2 Control Register T2CON
Defines Timer 2 operation
TIMER/COUNTER UNIT
Figure 9-6.Timer 2 Control Register
Timer Count Register
Contains the current timer count
T0CNT, T1CNT, T2CNT
TIMER/COUNTER UNIT
9.2.1Initialization Sequence
9.2.2Clock Sources
9.2.3Counting Modes
TIMER/COUNTER UNIT
Table 9-1.Timer 0 and 1 Clock Sources
TIMER/COUNTER UNIT
9.2.3.1Retriggering
9.2.4Pulsed and Variable Duty Cycle Output
TIMER/COUNTER UNIT
Table 9-2.Timer Retriggering
9.2.5Enabling/Disabling Counters
Timer Serviced 1
Internal Count Value
Maxcount -
9.2.6Timer Interrupts
9.3.1Input Setup and Hold Timings
9.2.7Programming Considerations
9.3TIMING
9.3.2Synchronization and Maximum Frequency
9.3.3Real-TimeClock
9.3.4Square-WaveGenerator
9.3.5Digital One-Shot
TIMER/COUNTER UNIT
Example 9-1.Configuring a Real-TimeClock
TIMER/COUNTER UNIT
TIMER/COUNTER UNIT
enable interrupts
TIMER/COUNTER UNIT
Example 9-2.Configuring a Square-WaveGenerator
TIMER/COUNTER UNIT
Example 9-3.Configuring a Digital One-Shot
TIMER/COUNTER UNIT
Page
Direct Memory Access Unit
Page
CHAPTER DIRECT MEMORY ACCESS UNIT
10.1 FUNCTIONAL OVERVIEW
10.1.1 The DMA Transfer
Fetch
10.1.2 Source and Destination Pointers
10.1.3 DMA Requests
10.1.4 External Requests
Fetch Cycle
10.1.5.1Timer 2-InitiatedTransfers
10.1.5 Internal Requests
10.1.6 DMA Transfer Counts
DIRECT MEMORY ACCESS UNIT
10.1.7.1Termination at Terminal Count
10.1.7.2Software Termination
10.1.8 DMA Unit Interrupts
10.1.9 DMA Cycles and the BIU
10.1.10 The Two-ChannelDMA Unit
Module
10.2 PROGRAMMING THE DMA UNIT
10.2.1 DMA Channel Parameters
DxSRCH
Register Name:DMA Source Address Pointer High
Register Mnemonic
DxSRCL
Register Name:DMA Source Address Pointer Low
Register Mnemonic
DIRECT MEMORY ACCESS UNIT
Register Mnemonic
DxDSTH
Register Function
DxDSTL
Register Name:DMA Destination Address Pointer Low
Register Mnemonic
DMA Control Register
DxCON
Controls DMA channel parameters
DIRECT MEMORY ACCESS UNIT
DIRECT MEMORY ACCESS UNIT
Register Name
DMA Control Register
Register Mnemonic
Register Name
DMA Control Register
Register Mnemonic
DxCON
DIRECT MEMORY ACCESS UNIT
10.2.1.4Arming the DMA Channel
10.2.1.5Selecting Channel Synchronization
10.2.1.6Programming the Transfer Count Options
DMA Transfer Count
DxTC
Contains the DMA channel’s transfer count
Register Name
10.2.2 Suspension of DMA Transfers
10.2.3 Initializing the DMA Unit
10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT
10.3.1 DRQ Pin Timing Requirements
10.3.2 DMA Latency
10.3.3 DMA Transfer Rates
10.3.4 Generating a DMA Acknowledge
10.4 DMA UNIT EXAMPLES
DIRECT MEMORY ACCESS UNIT
Example 10-1.Initializing the DMA Unit
DIRECT MEMORY ACCESS UNIT
Example 10-1.Initializing the DMA Unit Continued
DIRECT MEMORY ACCESS UNIT
Example 10-1.Initializing the DMA Unit Continued
SECTORS
DIRECT MEMORY ACCESS UNIT
Example 10-2.Timed DMA Transfers
DIRECT MEMORY ACCESS UNIT
Example 10-2.Timed DMA Transfers Continued
Page
Math Coprocessing
Page
CHAPTER MATH COPROCESSING
11.1 OVERVIEW OF MATH COPROCESSING
11.2 AVAILABILITY OF MATH COPROCESSING
11.3 THE 80C187 MATH COPROCESSOR
11.3.1 80C187 Instruction Set
•the 80C187 uses register or memory operands
MATH COPROCESSING
Table 11-2.80C187 Arithmetic Instructions
Addition
Division
MATH COPROCESSING 11.3.1.3Comparison Instructions
Table 11-3.80C187 Comparison Instructions
11.3.1.4Transcendental Instructions
Table 11-4.80C187 Transcendental Instructions
MATH COPROCESSING 11.3.1.5Constant Instructions
Table 11-5.80C187 Constant Instructions
11.3.1.6Processor Control Instructions
Table 11-6.80C187 Processor Control Instructions
11.3.2 80C187 Data Types
11.4 MICROPROCESSOR AND COPROCESSOR OPERATION
MATH COPROCESSING
Figure 11-1. 80C187-SupportedData Types
MATH COPROCESSING
80C187
Modular
Core
11.4.2 Processor Bus Cycles Accessing the 80C187
11.4.1 Clocking the 80C187
MATH COPROCESSING
Table 11-7.80C187 I/O Port Assignments
11.4.3 System Design Tips
MATH COPROCESSING
80C187
Modular
Core
11.4.4 Exception Trapping
11.5 EXAMPLE MATH COPROCESSOR ROUTINES
MATH COPROCESSING
80C186
Modular Core
80C187
MATH COPROCESSING
MATH COPROCESSING
ONCE Mode
Page
CHAPTER ONCE MODE
12.1 ENTERING/LEAVING ONCE MODE
ONCE MODE
Figure 12-1.Entering/Leaving ONCE Mode
bidirectional weakly held pins except OSCOUT
NOTES: 1. Entering ONCE Mode 2.Latching ONCE Mode
80C186 Instruction Set Additions and Extensions
Page
A.1 80C186 INSTRUCTION SET ADDITIONS
A.1.1 Data Transfer Instructions
PUSHA/POPA
A.1.2 String Instructions
INS source_string, port
OUTS port, destination_string
A.1.3 High-LevelInstructions
1.Main has variables at fixed locations
Figure A-2.Variable Access in Nested Procedures
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
Figure A-3.Stack Frame for Main at Level
BPA = BP Value for Procedure A
Figure A-4.Stack Frame for Procedure A at Level
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
BP SP
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
BP SP
Old BP BPM BPM BPM BPA BPA BPM BPA BPB
Display B Dynamic Storage B
LEAVE
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
BOUND register, address
A.2 80C186 INSTRUCTION SET ENHANCEMENTS
A.2.1 Data Transfer Instructions
PUSH data
A.2.2 Arithmetic Instructions
IMUL destination, source, data
A.2.3 Bit Manipulation Instructions
SAL destination, count
ROL destination, count
ROR destination, count
RCL destination, count
RCR destination, count
Input Synchronization
Page
B.1 WHY SYNCHRONIZERS ARE REQUIRED
APPENDIX B INPUT SYNCHRONIZATION
B.2 ASYNCHRONOUS PINS
Instruction Set Descriptions
Page
APPENDIX C INSTRUCTION SET DESCRIPTIONS
Table C-1.Instruction Format Variables
INSTRUCTION SET DESCRIPTIONS
Table C-2.Instruction Operands
Operand
Description
INSTRUCTION SET DESCRIPTIONS
Table C-3.Flag Bit Functions
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
ADC dest, src
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
Name
Description
Call Procedure
CALL procedure-name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
Clear Interrupt-enableFlag
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-10
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-11
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-12
Name
When Source Operand is a Byte
When Source Operand is a Word
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
Procedure Entry
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-14
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-15
Name
When Source Operand is a Byte
When Source Operand is a Word
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-17
IN accum, port
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-18
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-19
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-20
JA disp8
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
JAE disp8
JNB disp8
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
JE disp8
JZ disp8
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
JL disp8
JGE disp8
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
JNE disp8
JNZ disp8
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
JO disp8
JP disp8
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-26
LDS dest, src
Load Pointer Using ES
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-27
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-28
LODS src-string
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-29
MOV dest, src
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-30
MOVS dest-string, src-string
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-31
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-32
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-33
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-34
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-35
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-36
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-37
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-38
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-39
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
SHL dest, count
SAL dest, count
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-41
Name
When Source Operand is a Byte
When Source Operand is a Word
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-43
SHR dest, src
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-44
STOS dest-string
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-45
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-46
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-47
Name
Page
Instruction Set Opcodes and Clock Cycles
Page
APPENDIX D INSTRUCTION SET OPCODES
AND CLOCK CYCLES
Table D-1.Operand Variables
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary
Function
Format
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary Continued
DATA TRANSFER INSTRUCTIONS Continued
ARITHMETIC INSTRUCTIONS
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary Continued
ARITHMETIC INSTRUCTIONS Continued
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary Continued
ARITHMETIC INSTRUCTIONS Continued
BIT MANIPULATION INSTRUCTIONS
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary Continued
BIT MANIPULATION INSTRUCTIONS Continued
Shifts/Rotates
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary Continued
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary Continued
PROGRAM TRANSFER INSTRUCTIONS Continued
Iteration Control
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary Continued
Table D-3.Machine Instruction Decoding Guide
Byte
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-4.Mnemonic Encoding Matrix Left Half
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-4.Mnemonic Encoding Matrix Right Half
D-21
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Abbr
Definition
Abbr
Index
Page
INDEX
ARDY, See READY Arithmetic
INDEX
Crystal‚ See Oscillator
Data bus, See Address and data bus
INDEX
See also Bus cycles
See also Refresh Control Unit
Index-3
INDEX
Index-4
interrupt
INDEX
Index-5
INDEX
Index-6
Timers‚ See Timer Counter Unit TCU
INDEX
Index-7
INDEX
Index-8
