Intel 80C188XL, 80C186XL 8.5SLAVE MODE, Register Name Register Mnemonic Register Function

INTERRUPT CONTROL UNIT

Register Name:

Register Mnemonic:

Register Function:

15

D

H

L

T

Interrupt Status Register

INTSTS

Indicates pending shared-source interrupts and DMA suspension

		0
T	T	T
M	M	M
R	R	R
2	1	0

A1193-A0

Bit	Bit Name	Reset	Function
Mnemonic		State
DHLT	DMA Halt	0	This bit is set to suspend DMA activity.
TMR2:0	Timer	000	A bit is set to indicate a pending interrupt from
	Interrupt		the corresponding timer.
	Pending

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 8-14. Interrupt Status Register

NOTE

Do not write to the DHLT bit while Timer/Counter Unit interrupts are enabled. A conflict with the internal use of the register may cause incorrect processing of timer interrupts.

The DHLT bit does not function when the interrupt controller is in slave mode.

8.5SLAVE MODE

Although Master mode is the most common, Slave mode is useful in larger system designs. In Slave mode, an external 8259A module controls the interrupt input to the CPU and acts as the master interrupt controller. The Interrupt Control Unit processes only the internal interrupt re- quests and acts as an interrupt input to the external 8259A. In simplest terms, the Interrupt Control Unit behaves like a cascaded 8259A to the master 8259A. (See Figures 8-15 and 8-16.)

8-23