Intel 80C186XL RD, W R Float BHE , S20, Lock, Hold Bus Latency, Signal Hold Condition

BUS INTERFACE UNIT

CLKOUT
1
HOLD	4
2
HLDA
	3
AD15:0	Float
DEN
A19:16
RD, WR,	Float
DT/R,
BHE, S2:0
LOCK
NOTES:
1. THVCL : HOLD input to clock low
2. TCHCZ : Clock high to output float
3. TCLAZ : Clock low to output float
4. TCLHAV : Clock low to HLDA high
	A1518-0A

Figure 3-34. Timing Sequence Entering HOLD

Table 3-8. Signal Condition Entering HOLD

				Signal			HOLD Condition
A19:16,							These signals float one-half clock before HLDA
	S2:0,	RD,	WR,	DT/R,	BHE (RFSH), LOCK
							is generated (i.e., phase 2).
AD15:0 (16-bit), AD7:0 (8-bit), A15:8 (8-bit),							These signals float during the same clock in
						DEN
							which HLDA is generated (i.e., phase 1).

3.7.1.1HOLD Bus Latency

The duration between the time that the external device asserts HOLD and the time that the BIU asserts HLDA is known as bus latency. In Figure 3-34, the two-clock delay between HOLD and HLDA represents the shortest bus latency. Normally this occurs only if the bus is idle or halted or if the bus hold request occurs just before the BIU begins another bus cycle.

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