Intel 80C188XL, 80C186XL user manual The chip-selectis enabled

CHIP-SELECT UNIT

By combining LCS, UCS and MCS3:0, you can cover up to 786 Kbytes of memory address space. Methods such as those shown in Figure 6-1 on page 6-2 can be used to decode the remaining 256 Kbytes.

The PCS6:0 chip-selects access a contiguous, 896-byte block of memory or I/O address space. Each chip-select goes active for one-seventh of the block (128 bytes). The start address is pro- grammed in the PACS register (Figure 6-8 on page 6-10); it can begin on any 1 Kbyte boundary.

A chip-select goes active when it meets all of the following criteria:

1.The chip-select is enabled.

2.The bus cycle status matches the default or programmed type (memory or I/O).

3.The bus cycle address is within the default or programmed block size.

4.The bus cycle is not accessing the Peripheral Control Block.

A memory address applies to memory read, memory write and instruction prefetch bus cycles. An I/O address applies to I/O read and I/O write bus cycles. Interrupt acknowledge and HALT bus cycles never activate a chip-select, regardless of the address generated.

After power-on or system reset, only the UCS chip-select is initialized and active (see Figure 6-4).

1Address

SRDY

ARDY

UCS

Processor

UCS

Data

Active For

Top 1 KByte

Memory

Map

1MB

1023K

0

NOTE:

1. 3 wait states automatically inserted. Bus READY must be provided.

A1006-0A

Figure 6-4. UCS Reset Configuration

6-5