Intel 80C188XL DMA Transfer Count, DxTC, Contains the DMA channel’s transfer count, Register Name

	DIRECT MEMORY ACCESS UNIT
Register Name:	DMA Transfer Count
Register Mnemonic:	DxTC
Register Function:	Contains the DMA channel’s transfer count.

15

T	T	T	T
C	C	C	C
1	1	1	1
5	4	3	2

T

C

1

1

TT C C

19

T

C

8

T	T	T	T
C	C	C	C
7	6	5	4

			0
T	T	T	T
C	C	C	C
3	2	1	0

A1172-0A

Bit	Bit Name	Reset	Function
Mnemonic		State
TC15:0	Transfer	XXXXH	Contains the transfer count for a DMA channel.
	Count		This value is decremented by one after each
			transfer.

Figure 10-12. Transfer Count Register

The TC bit, when set, instructs the DMA channel to disarm itself (by clearing the STRT bit) when the transfer count reaches zero. If the TC bit is cleared, the channel continues to perform transfers regardless of the state of the Transfer Count Register. Unsynchronized (software-initiated) trans- fers always terminate when the transfer count reaches zero; the TC bit is ignored.

10.2.1.7Generating Interrupts on Terminal Count

A channel can be programmed to generate an interrupt request whenever the transfer count reach- es zero. Both the TC bit and the INT bit in the DMA Control Register (Figure 10-11 on page 10-15) must be set to generate an interrupt request.

10.2.1.8Setting the Relative Priority of a Channel

The priority of a channel is controlled by the Priority bit in the DMA Control Register (Figure 10-11 on page 10-15). A channel may be assigned either high or low priority. If both channels are programmed to the same priority (i.e., both high or both low), the channels rotate priority.

10-19