Intel 80C188XL, 80C186XL 3.7.2Exiting HOLD, +5 HLDA RESET HOLD, Pre Dq Clr, Latched HLDA

BUS INTERFACE UNIT

+5

HLDA

RESET

HOLD

PRE

DQ

CLR

Latched HLDA

A1535-0A

Figure 3-36. Latching HLDA

The removal of HOLD must be detected for at least one clock cycle to allow the BIU to regain the bus and execute a refresh bus cycle. Should HOLD go active before the refresh bus cycle is complete, the BIU will release the bus and generate HLDA.

3.7.2Exiting HOLD

Figure 3-37 shows the timing associated with exiting the bus hold state. Normally a bus operation (e.g., an instruction prefetch) occurs just after HOLD is released. In a 16-bit bus system, the upper half of the bus (D15:8) floats.

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