Hlda Reset Hold PRE CLR, Latched Hlda | Intel 80C188XL, 80C186XL

BUS INTERFACE UNIT

+5

HLDA

RESET

HOLD

PRE

DQ

CLR

Latched HLDA

A1535-0A

Figure 3-36. Latching HLDA

The removal of HOLD must be detected for at least one clock cycle to allow the BIU to regain the bus and execute a refresh bus cycle. Should HOLD go active before the refresh bus cycle is complete, the BIU will release the bus and generate HLDA.

3.7.2Exiting HOLD

Figure 3-37 shows the timing associated with exiting the bus hold state. Normally a bus operation (e.g., an instruction prefetch) occurs just after HOLD is released. In a 16-bit bus system, the upper half of the bus (D15:8) floats.

3-43

Image 124

Intel 80C188XL, 80C186XL user manual Hlda Reset Hold PRE CLR, Latched Hlda, Exiting Hold

Contents

80C186XL/80C188XL Microprocessor User’s Manual 80C186XL/80C188XL Microprocessor User’s Manual Intel Corporation Contents Contents Setting the PCB Base Location Power ManagementClock Generation LCS Chapter Refresh Control Unit Programming the Interrupt Control Unit Functional Overview Programming the TIMER/COUNTER UnitFunctional Overview Chapter Math Coprocessing Chapter Once Mode Figures Reset Configuration UCS Interrupt Control Register for Noncascadable External Pins 10-9 Tables Flag Bit Functions Examples Example Introduction Page Chapter Introduction Feature 80C186XL 80C186EA 80C186EB 80C186EC HOW to USE this ManualComparison of 80C186 Modular Core Family Products Related Documents and Software Related DocumentsDocument/Software Title Order No FaxBack Service Electronic Support Systems Bulletin Board System BBS World Wide Web CompuServe ForumsTechnical Support Product Literature Training ClassesPage Overview 80C186 Family Architecture Page Chapter Overview of the 80C186 Family Architecture Architectural Overview Simplified Functional Block Diagram of the 80C186 Family CPU Execution Unit Bus Interface Unit Physical Address Generation General Registers General Registers Implicit Use of General Registers Segment RegistersOperations Instruction Pointer Segment Registers Flags Memory Segmentation Register Name Register MnemonicPSW Flags Register Function Logical Addresses Segment Locations in Physical Memory Data DS Code CS Stack SS Extra ES Fffffh 2BFH 2BEH 2BDH 2BCH 2BBH 2BAH Dynamically Relocatable Code Type of Memory Reference Default Alternate OffsetLogical Address Sources Segment Code Data Before After Relocation Code SegmentSegment Data Extra Stack Implementation Reserved Memory and I/O Space 10. Stack Operation Software Overview Instruction Set General-Purpose Data Transfer InstructionsInput/Output Lahf S Z U a U P U C Sahf 7 6 5 4 3 2 1Pushf Popf U U O D I T S Z U a U P U C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Addition SubtractionMultiplication Division Arithmetic Interpretation of 8-Bit Numbers Bit Manipulation InstructionsHex Bit Pattern Unsigned Signed Unpacked Packed Binary Shifts String Instructions Program Transfer Instructions String Instruction Register and Flag UseCX AL/AX Overview of the 80C186 Family Architecture Conditional Transfers Unconditional TransfersIteration Control Interrupts 10. Interpretation of Conditional Transfers Mnemonic Condition Tested Jump if… Addressing Modes Processor Control Instructions11. Processor Control Instructions Register and Immediate Operand Addressing Modes Memory Addressing Modes 0000 Physical Addr BIU Opcode Mod R/M Displacement 13. Direct Addressing 14. Register Indirect Addressing 15. Based Addressing Displacement High Address Rate Age Rate Base VacBase Register Register Dept Div Employee Age 18. Accessing an Array with Indexed Addressing 17. Indexed Addressing 19. Based Index Addressing 20. Accessing a Stacked Array with Based Index Addressing Opcode Source EA Destination EA Data Types Used in the 80C186 Modular Core Family 12. Supported Data TypesType Description BCD 23 C186 Modular Core Family Supported Data Types Interrupts and Exception Handling Interrupt/Exception Processing 3FE 3FC Overview of the 80C186 Family Architecture Interrupt Enable Bit StackPSW Trap Flag Maskable Interrupts Exceptions Invalid Opcode Type Software Interrupts Interrupt Latency Interrupt Response Time ClocksTotal Interrupt and Exception Priority NMI Execute Divide Service RoutineIret Trap Flag = ??? 29. Simultaneous NMI and Single Step Interrupts Interrupt Enable Bit IE = Trap Flag TF = 30. Simultaneous NMI, Single Step and Maskable InterruptPage Bus Interface Unit Page Address and Data BUS Concepts Multiplexed Address and Data BUS1 16-Bit Data Bus Physical Implementation Address Space for MByte KBytesFffff Ffffe Ffffd Ffffc A190 D70 A191 D158 Even Byte Transfer A191 D158 BHE HighOdd Byte Transfer D70 A0 Low A191 D158 BHE High A191 D158 BHE Low D70 A0 Low Bit Data Bus Even Word Transfers First Bus Cycle A191 D158 BHE LowSecond Bus Cycle D70 A0 High A191 D158 BHE Low Memory and I/O Interfaces Bit Data Bus Word Transfers 2 8-Bit Bus Memory and I/O Requirements 1 16-Bit Bus Memory and I/O RequirementsBUS Cycle Operation Phase Low Phase High PhaseClkout ALE S20 Valid Status AD150 Address Data Bus Ready Request PendingHold Deasserted RES# Address Status Phase Or TW Or TI Data Phase Address/Status PhaseOr TI Clkout A1916 S20 STB ALE STB Data Phase Wait States Clkout RD/ WR Or TW Or TIAD150 Valid Write Data Read Read Data S20 Ardy Clkout Srdy ReadyBUS Ready CS1 CS2 CS3 CS4 ALE Clkout 16. Generating a Normally Ready Bus Signal Clock Clkout Ardy Srdy Idle States 18. Normally Ready System Timings BUS Cycles Read Bus CyclesRead Bus Cycle Types Read Cycle Critical Timing Parameters A158 RfshA150 DT/R DEN UCS AD70 O0-727C256 LA151 AD158 Write Bus Cycle Types A158 A150Status Bits Bus Cycle Type LA151 LA0 BHEA014 O18 CS1 AD70 AD158 LCS Interrupt Acknowledge Bus Cycle Write Cycle Critical Timing Parameters Lock DT/R DEN INTA0 INTA1BHE RD, WR INTA0 Inta INT0 IR0 IR7 PCS0 LA1 Processor 82C59ASystem Design Considerations Halt Bus Cycle Pins Pin State 011 AD150 AD70 A158 A1916Rfsh = BHE Temporarily Exiting the Halt Bus State Clkout Hold HldaAD150 AD70 A158 A1916 Control S20 AD150 AD70 A158 A1916 BHE Rfsh T4 T1 T2 T3 T3 TI TI TI TIAD70 A158 RFSH=1 NMI/INTx System Design Alternatives Buffering the Data Bus Clkout RD,WR DT/R DEN DT/ R DeviceCPU Local Bus Buffered Bus MCS0 Buffer Buffered Data Bus AD70Buffer Local Data Bus Synchronizing Software and Hardware Events Using a Locked Bus Using the Queue Status Signals Queue Status Signal DecodingQueue Status No queue operation occurred MULTI-MASTER BUS System Designs Entering Bus Hold Signal Hold Condition FloatRD, W R Float BHE , S20 Lock Refresh Operation During a Bus Hold BHE, S20 Clkout Hold Hlda DEN RD, WRDT/R Lock Latched Hlda Hlda Reset Hold PRE CLRExiting Hold DT/R, S20 A1916, Lock DEN RD, WR, BHEBUS Cycle Priorities BUS Interface Unit Page Peripheral Control Block Page Peripheral Control Registers PCB Relocation Register Register Name PCB Relocation Register Register Mnemonic Bit Bit Name Reset Function Mnemonic StateRelreg Peripheral Control Block Accessing the Peripheral Control Block Ready Signals and Wait StatesReserved Locations Bus Cycles Bus Operation Word reads Setting the PCB Base Location Accessing the Peripheral Control RegistersAccessing Reserved Locations Writing the PCB Relocation Register Considerations for the 80C187 Math Coprocessor Interface Page Clock Generation Power Management Page RES Clock GenerationCrystal Oscillator = Inverter Output Z 90˚ 180˚ Oscillator Operation Crystal Connections to Microprocessor Third-Overtone Crystal Inductor L1 Values µH Selecting Crystals Reset and Clock Synchronization Using an External OscillatorOutput from the Clock Generator Typical Ct = V 1 e 1µf typical Cold Reset Waveform PCS60,NCS Clkout Power Management Clkout ResetRES Resync Power-Save Mode Entering Power-Save Mode Power Save Register Enables and sets clock division factorRegister Name Register Mnemonic Register Function Pwrsav 10. Power-Save Clock Transition Leaving Power-Save Mode Example Power-Save Initialization Code Syntax Chip-Select Unit Page CHIP-SELECT Unit Features and Benefits Common Methods for Generating CHIP-SELECTS Chip-Selects Using Addresses Directly Simple Decoder CHIP-SELECT Unit Functional Overview27C256 74AC138 MCS3 MCS2MCS1 PCS1 A1916 UCS, PC S60 MCS30, LCS 1Address Srdy Ardy UCSData Active For Top 1 KByte Memory Map 1MB Programming Initialization SequenceChip-Select Unit Registers Control Register Alternate Register Umcs UCS Control RegisterControls the operation Chip-select LCS Control Register Lmcs MCS Control Register MmcsControls the operation Chip-selects MCS Pacs PCS Control RegisterPCS Mpcs Register NameMCS and PCS Alternate Control RegisterX S Programming the Active Ranges UCS Active RangeUCS Block Size and Starting Address Umcs Field Block Size Starting Address U1710 LCS Active Range LCS Active RangeMCS Active Range Lmcs Field Block Size Ending Address U1710 MCS Block Size and Start Address Restrictions Block Size Mmcs Start Address Kbytes Restrictions Bus Wait State and Ready Control PCS Active Range Wait State Ready R2 Control Bit Wait Wait State Value R10 State CounterOverlapping Chip-Selects Memory or I/O Bus Cycle Decoding Programming Considerations CHIP-SELECTS and BUS Hold Example 1 Typical System ConfigurationExamples 13. Typical System Example 6-1. Initializing the Chip-Select Unit MOD186XREF Name CSUEXAMPLE1 Drambase EQU Place memory variables here Refresh Control Unit Page CPU CLR REQ Refresh Control Unit Capabilities Role of the Refresh Control UnitRefresh Control Unit Operation Refresh Control Unit Operation Flow Chart Refresh Addresses Refresh Address Formation Refresh BUS Cycles Guidelines for Designing Dram ControllersIdentification of Refresh Bus Cycles Data Bus Width Muxed Row Column Address S20 T3/TW ClkoutRAS CAS Calculating the Refresh Interval Programming the Refresh Control UnitRefresh Control Unit Registers Register NameRefresh Base Address Register RfbaseRegister FunctionDetermines upper 7 bits of refresh address Refresh Base Address Register Rftime Register Function Sets refresh rate Refresh Control Register RfconControls Refresh Unit operation Programming Example Example 7-1. Initializing the Refresh Control Unit Refresh Operation and BUS Hold Clkout Hold Hlda DEN RD, WR BHE, S2 DT / R A1916Page Interrupt Control Unit Page Chapter Interrupt Control Unit Functional Overview Master Mode Timer 0 Timer 1 TimerGeneric Functions in Master Mode DMA Default Interrupt Priorities Interrupt MaskingInterrupt Priority Interrupt Name Relative Priority Interrupt Nesting Priority Resolution Functional Operation in Master ModeTypical Interrupt Sequence Priority Resolution Example Cascading with External 8259As Interrupts That Share a Single Source INT INT0 Inta INTA0INT INT1 Inta INTA1 Interrupt Acknowledge Sequence PollingFixed Interrupt Types Interrupt Name Interrupt Type Edge and Level Triggering Additional Latency and Response Time Inta Idle Inta Idle Read IPRead CS Idle Push Flags Push CS Push IP Programming the Interrupt Control Unit 2CH Interrupt Control Registers2AH Interrupt Control Register for Internal Sources MSK I2CON, I3CON Register NameInterrupt Control Register non-cascadable pinsLVL Register NameInterrupt Control Register cascadable pins I0CON, I1CONSfnm CAS Interrupt Request Register Register Name Interrupt Request Register Register MnemonicReqst Register Function Stores pending interrupt requests Register Name Interrupt Mask Register Register Mnemonic ImaskRegister Function Masks individual interrupt sources Priority Mask Register In-Service Register Priority Mask RegisterPrimsk Masks lower-priority interrupt sources In-Service Register InservIndicates which interrupt handlers are in process Poll and Poll Status Registers Poll Poll RegisterIreq Read to check for pending interrupts when polling Poll Status RegisterPollsts End-of-Interrupt EOI Register Used to issue an EOI command End-of-Interrupt RegisterEOI Interrupt Status Register Slave Mode Interrupt Status RegisterIntsts Dhlt INT0 Inta IRQ INT VCC Slave Mode Programming 16. Interrupt Sources in Slave Mode Slave Mode Fixed Interrupt Type Bits Master Mode Slave Mode PCB Offset Register NameInterrupt Vector Register Interrupt Control Unit Register Comparison Register NameInterrupt Vector Register Slave Mode only Intvec End-of-Interrupt Register in Slave Mode Used to issue the EOI command Interrupt Vectoring in Slave Mode T1 T2 T3 T4Inta INTA0 Select Lock CAS20 Slave Cascade Address From 8259A Initializing the Interrupt Control Unit for Master Mode Inta Idle Read IP Read CS Push Flags Push CS Push IP Priorities are used Page Timer/Counter Unit Page Chapter TIMER/COUNTER Unit Timer Element Registers Output Latch Interrupt Latch Clock Counter Element Multiplexing and Timer Input Synchronization T0IN T1IN T0OUT T1OUT Timers 0 and 1 Flow Chart From Programming the TIMER/COUNTER Unit Timer/Counter Unit Output Modes Defines Timer 0 and 1 operation Timer 0 and 1 Control RegistersT0CON, T1CON RTG EXTALT Cont Timer 2 Control Register Defines Timer 2 operationT2CON Maximum count. The MC bit must be cleared Register Name Timer Count Register Register Mnemonic Register Function Contains the current timer countT0CNT, T1CNT, T2CNT C C Timer Maxcount Compare Registers Timer 0 and 1 Clock Sources Clock SourcesCounting Modes Clock Source Retriggering Timer Operation Timer RetriggeringPulsed and Variable Duty Cycle Output Timer Serviced Internal Count Value Maxcount TxOUT Pin Enabling/Disabling Counters Input Setup and Hold Timings Timer InterruptsTiming Timer/Counter Unit Application Examples Synchronization and Maximum FrequencyReal-Time Clock Square-Wave Generator Example 9-1. Configuring a Real-Time Clock Intsts Out Dx, al Timer2interruptroutine proc far Example 9-2. Configuring a Square-Wave Generator T1CON Example 9-3. Configuring a Digital One-Shot Cmpb Page Direct Memory Access Unit Page Chapter Direct Memory Access Unit DMA Transfer Fetch Deposit Typical DMA Transfer Source and Destination Pointers DMA RequestsDMA Transfer Directions Byte and Word Transfers External Requests T1 or T2 or T3 or TW or T4 orCycle DRQ DRQ Case Source Synchronization Timer 2-Initiated Transfers Fetch Cycle Deposit Cycle T1 T2 T3 T4 T1 T2 T3 T4 TI TIClkout DRQ Case DMA Transfer Counts Termination and Suspension of DMA Transfers DMA Unit Interrupts DMA Cycles and the BIUTwo-Channel DMA Unit DMA Channel Arbitration Module Two-Channel DMA Module Programming the DMA Unit SRCDMA Channel Parameters Register Mnemonic DxSRCH Register NameDMA Source Address Pointer HighDMA Xxxxh Register Mnemonic DxSRCL Register NameDMA Source Address Pointer LowS S a a DxDSTH Register NameDMA Destination Address Pointer HighContains the upper 4 bits of the DMA Destination pointer Register NameDMA Destination Address Pointer Low Register Mnemonic DxDSTL D I E N C C C N T DmemDdec Dinc Synchronization Type Idrq Strt CHGWord Selecting Channel Synchronization Arming the DMA ChannelProgramming the Transfer Count Options Setting the Relative Priority of a Channel Generating Interrupts on Terminal Count Suspension of DMA Transfers Initializing the DMA UnitHardware Considerations and the DMA Unit DRQ Pin Timing Requirements DMA Latency DMA Transfer Rates Generating a DMA Acknowledge DMA Unit Examples Example 10-1. Initializing the DMA Unit MOV DS, AX Assume Dsdataseg 10-24 10-25 Example 10-2. Timed DMA Transfers 10-27 Page Math Coprocessing Page Overview of Math Coprocessing Availability of Math Coprocessing 80C187 Math Coprocessor 11.3.1 80C187 Instruction Set C187 Data Transfer Instructions Real TransfersInteger Transfers Packed Decimal Transfers C187 Arithmetic Instructions Other Operations Comparison Instructions C187 Comparison InstructionsTranscendental Instructions C187 Transcendental Instructions Constant Instructions C187 Constant InstructionsC187 Processor Control Instructions Fldz FLD1 Fldpi FLDL2T FLDL2E FLDLG2 FLDLN2 11.3.2 80C187 Data Types Microprocessor and Coprocessor Operation C187-Supported Data Types Modular Core 80C18780C186 Processor Bus Cycles Accessing the 80C187 Clocking the 80C187C187 I/O Port Assignments Address Read Definition Write Definition System Design Tips C187 Configuration with a Partially Buffered Bus Exception Trapping Example Math Coprocessor Routines 80C186 Modular Core C187 Exception Trapping via Processor Interrupt Pin Name Example80C187init Example 11-2. Floating Point Math Routine Using Fsincos Results Once Mode Page Chapter Once Mode ENTERING/LEAVING Once Mode RES UCS LCS Oscout 80C186 Instruction Set Additions Extensions Page 80C186 Instruction SET Additions Data Transfer Instructions String Instructions High-Level Instructions Figure A-1. Formal Definition of Enter Figure A-2. Variable Access in Nested Procedures Figure A-4. Stack Frame for Procedure a at Level BPM BPA BPB Leave Bound register, address 80C186 Instruction SET Enhancements Bit Manipulation Instructions Arithmetic InstructionsShift Instructions ROL destination, count Rotate Instructions Input Synchronization Page WHY Synchronizers are Required Figure B-1. Input Synchronization Circuit Asynchronous Pins Instruction Set Descriptions Page Table C-1. Instruction Format Variables Variable Description Table C-2. Instruction Operands Operand Description Table C-3. Flag Bit Functions Table C-4. Instruction Set Ascii Adjust for Subtraction AASADC Add with Carry ADD ADD dest, srcLogical Dest, src Call Procedure Call procedure-nameBound Detect Value Out of Range Clear Carry flag Convert Byte to WordClear Direction flag Clear Interrupt-enable Flag Complement Carry Flag CMP CompareCMP dest, src Compare String Decimal Adjust for Subtraction Decimal Adjust for AdditionConvert Word to Doubleword DEC Decrement Divide When Source Operand is a Byte When Source Operand is a Word Enter locals, levels Procedure EntryEscape Halt Integer Divide When Source Operand is a Byte Integer Multiply When Source Operand is a Byte Input Byte or Word When Source Operand is a ByteImul Accum, port INC IncrementString INS dest-string, port Interrupt INT interrupt-type Interrupt on Overflow Interrupt ReturnJump on Above Jump on Not Below or Equal Jump on Above or Equal Jump on Not BelowJump on Below Jump on Not Above or Equal Jump if CX Zero Jump on Equal Jump on ZeroJump on Greater Than Jump on Not Less Than or Equal Name Description Operation Flags Affected Jump on Less Than Jump on Not Greater Than or EqualJump on Less Than or Equal Jump on Not Greater Than Jump on Not Equal Jump on Not ZeroJump on Not Overflow Jump on Not Sign Name Description Operation Flags Affected Jump on Overflow Jump on ParityJump on Parity Equal Instruction Format Load Pointer Using DS LDS dest, srcLoad Effective Address LEA dest, src LES dest, src Load Pointer Using ESLock the Bus Load String Byte or Word When Source Operand is a Byte Lods src-stringLoop Loop While Equal Loop While Not Equal Loop While Not ZeroMove Byte or Word MOV dest, src Multiply When Source Operand is a Byte Move StringMovs dest-string, src-string MUL Logical Not When Source Operand is a Byte Negate When Source Operand is a ByteNEG Name Description Operation Flags Affected Logical or Or dest,srcOutput OUT port, accumulator Outs port, srcstring Out StringPop Pop Flags Pop AllPush Push All Push Flags Rotate Through Carry Left RCL dest, countRotate Through Carry Right RCR dest, count Repeat Repeat While EqualRepeat While Zero Repeat While Not Equal RET ReturnRET optional-pop-value Rotate Left ROR dest, count Rotate RightStore Register AH Into Flags Shift Arithmetic Left Shift Logical LeftShift Arithmetic Right Subtract With Borrow SBBSBB dest, src Scan String When Source Operand is a Byte Scas dest-string Shift Logical Right SHR dest, srcSet Carry Flag Set Direction Flag Store Byte or Word String When Source Operand is a Byte Set Interrupt-enable FlagStos dest-string SUB SubtractSUB dest, src Test Exchange WaitXchg dest, src Translate Xlat translate-tableExclusive Or XOR dest, srcPage Instruction Set Opcodes and Clock Cycles Page Table D-1. Operand Variables EA CalculationMod Effect on EA Calculation Reg Bit w=1 Bit w=0 Table D-2. Instruction Set Summary Function Format Clocks Arithmetic Instructions Arithmetic Instructions BIT Manipulation Instructions String Manipulation Instructions JB/JNAE = LOOPNZ/LOOPNE = Table D-3. Machine Instruction Decoding Guide Processor Control Instructions Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles AX,CX Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles AL,DX Instruction SET Opcodes and Clock Cycles Table D-4. Mnemonic Encoding Matrix Left Half Table D-4. Mnemonic Encoding Matrix Right Half Table D-5. Abbreviations for Mnemonic Encoding Matrix Abbr Definition Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8