Intel 80C188XL, 80C186XL user manual Using a Locked Bus

BUS INTERFACE UNIT

The WAIT instruction suspends program execution until one of two events occurs: an interrupt is generated, or the TEST input pin is sampled low. Unlike interrupts, the TEST input pin does not require that program execution be transferred to a new location (i.e., an interrupt routine is not executed). In processing the WAIT instruction, program execution remains suspended as long as TEST remains high (at least until an interrupt occurs). When TEST is sampled low, program execution resumes.

The TEST input and WAIT instruction provide a mechanism to delay program execution until a hardware event occurs, without having to absorb the delay associated with servicing an interrupt.

3.6.3Using a Locked Bus

To address the problems of controlling accesses to shared resources, the BIU provides a hardware LOCK output. The execution of a LOCK prefix instruction activates the LOCK output.

LOCK goes active in phase 1 of T1 of the first bus cycle following execution of the LOCK prefix instruction. It remains active until phase 1 of T1 of the first bus cycle following the execution of the instruction following the LOCK prefix. To provide bus access control in multiprocessor sys- tems, the LOCK signal should be incorporated into the system bus arbitration logic residing in the CPU.

During normal multiprocessor system operation, priority of the shared system bus is determined by the arbitration circuits on a cycle by cycle basis. As each CPU requires a transfer over the sys- tem bus, it requests access to the bus via its resident bus arbitration logic. When the CPU gains priority (determined by the system bus arbitration scheme and any associated logic), it takes con- trol of the bus, performs its bus cycle and either maintains bus control, voluntarily releases the bus or is forced off the bus by the loss of priority.

The lock mechanism prevents the CPU from losing bus control (either voluntarily or by force) and guarantees that the CPU can execute multiple bus cycles without intervention and possible corruption of the data by another CPU. A classic use of the mechanism is the “TEST and SET semaphore,” during which a CPU must read from a shared memory location and return data to the location without allowing another CPU to reference the same location during the test and set operations.

Another application of LOCK for multiprocessor systems consists of a locked block move, which allows high speed message transfer from one CPU’s message buffer to another. During the locked instruction (i.e., while LOCK is active), a bus hold, DMA or refresh request is recorded, but is not acknowledged until completion of the locked instruction. However, LOCK has no effect on interrupts. As an example, a locked HALT instruction causes bus hold, DMA or refresh bus re- quests to be ignored, but still allows the CPU to exit the HALT state on an interrupt.

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