Intel 80C186XL Register Name Register Mnemonic Register Function, P S E N, 9. Power-SaveRegister

CLOCK GENERATION AND POWER MANAGEMENT

Register Name:

Register Mnemonic:

Register Function:

15

P

S

E

N

Power Save Register

PWRSAV

Enables and sets clock division factor.

0

F F 1 0

A1130-0A

Bit	Bit Name	Reset			Function
Mnemonic		State
PSEN	Power Save	0H	Setting this bit enables Power Save mode and
	Enable		divides the internal operating clock by the value
			defined by F1:0. Clearing this bit disables
			Power-Save mode and forces the CPU to
			operate at full speed. PSEN is automatically
			cleared whenever an interrupt occurs.
F1:0	Clock	0H	These bits control the clock division factor used
	Division		when Power Save mode is enabled. The
	Factor		allowable values are listed below:
			F1	F0 Divisor
			0	0	By 1 (undivided)
			0	1	By 4
			1	0	By 8
			1	1	By 16

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 5-9. Power-Save Register

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