Intel 80C188XL Timer 0 and 1 Control Registers, T0CON, T1CON, Defines Timer 0 and 1 operation

TIMER/COUNTER UNIT

Register Name:

Register Mnemonic:

Register Function:

15

E	I	I	R
N	N	N	I
	H	T	U

Timer 0 and 1 Control Registers

T0CON, T1CON

Defines Timer 0 and 1 operation.

					0
M	R	P	E	A	C
C	T		X	L	O
	G		T	T	N
					T

A1297-0A

Bit	Bit Name	Reset			Function
Mnemonic		State
EN	Enable	0	Set to enable the timer. This bit can be written only
			when the	INH	bit is set.
INH	Inhibit	X	Set to enable writes to the EN bit. Clear to ignore
			writes to the EN bit. The			INH	bit is not stored; it
			always reads as zero.
INT	Interrupt	X	Set to generate an interrupt request when the Count
			register equals a Maximum Count register. Clear to
			disable interrupt requests.
RIU	Register In	X	Indicates which compare register is in use. When set,
	Use		the current compare register is Maxcount Compare B;
			when clear, it is Maxcount Compare A.
MC	Maximum	X	This bit is set when the counter reaches a maximum
	Count		count. The MC bit must be cleared by writing to the
			Timer Control register. This is not done automati-
			cally. If MC is clear, the counter has not reached a
			maximum count.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 9-5. Timer 0 and Timer 1 Control Registers

9-7