Intel 80C188XL, 80C186XL user manual Memory or I/O Bus Cycle Decoding, Programming Considerations

CHIP-SELECT UNIT

For example, assume MCS3 overlaps UCS. MCS3 is programmed for two wait states and re- quires bus ready, while UCS is programmed for no wait states and ignores bus ready. An access to the overlapped region has two wait states and requires bus ready (the values programmed in the R2:0 bits in the MPCS register).

Be cautious when overlapping chip-selects with different wait state or bus ready programming. The following two conditions require special attention to ensure proper system operation:

1.When all overlapping chip-selects ignore bus ready but have different wait states, verify that each chip-select still works properly using the highest wait state value. A system failure may result when too few or too many wait states occur in the bus cycle.

2.If one or more of the overlapping chip-selects requires bus ready, verify that all chip- selects that ignore bus ready still work properly using both the smallest wait state value and the longest possible bus cycle. A system failure may result when too few or too many wait states occur in the bus cycle.

6.4.5Memory or I/O Bus Cycle Decoding

The UCS, LCS and MCS chip-selects activate only for memory bus cycles. The PCS chip-selects activate for either memory or I/O bus cycles, depending on the state of the MS bit in the MPCS register (Figure 6-9 on page 6-11). Memory bus cycles consist of memory read, memory write and instruction prefetch cycles. I/O bus cycles consist of I/O read and I/O write cycles.

Chip-selects go active for bus cycles initiated by the CPU, DMA Control Unit and Refresh Con- trol Unit.

6.4.6Programming Considerations

When programming the PCS chip-selects active for I/O bus cycles, remember that eight bytes of I/O are reserved by Intel. These eight bytes (locations 00F8H through 00FFH) control the inter- face to an 80C187 math coprocessor. A chip-select can overlap this reserved space provided there is no intention of using the 80C187. However, to avoid possible future compatibility issues, Intel recommends that the PCS chip-selects not start at I/O address location 0H.

Reading or writing the chip-select registers enables the corresponding chip-select. Reading a reg- ister before writing to it enables the chip-select without initializing the programmable fields, which causes indeterminate operation. For example, reading the LMCS register enables the LCS chip-select, but it does not ensure that LCS is programmed correctly. Once you enable a chip- select, you cannot disable it, but you can change its operation by writing to the appropriate reg- ister.

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