CHIP-SELECT UNIT

Register Name:

 

 

 

 

PCS Control Register

Register Mnemonic:

PACS

Register Function:

Controls the operation of the

 

chip-selects.

PCS

15

U

U

U

U

1

1

1

1

9

8

7

6

 

 

 

 

U U

11

54

U

1

3

 

 

 

0

 

R

R

R

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

A1143-0B

 

 

 

 

 

 

 

 

 

Bit

Bit Name

Reset

 

 

 

 

Function

 

Mnemonic

State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

U19:13

Start

XXH

 

Defines the starting address for the block of

 

 

Address

 

 

PCS

chip-selects. During memory or I/O bus

 

 

 

 

 

cycles, U19:13 are compared with the A19:13

 

 

 

 

 

address bits. An equal to or greater than result

 

 

 

 

 

enables the

PCS

chip-select. U19:16 must be

 

 

 

 

 

programmed to zero for proper I/O bus cycle

 

 

 

 

 

operation.

 

 

 

 

 

 

 

R2

Bus Ready

X

 

When R2 is clear, bus ready must be active to

 

 

Disable

 

 

complete a bus cycle. When R2 is set, R1:0

 

 

 

 

 

control the number of bus wait states and bus

 

 

 

 

 

ready is ignored.

 

 

 

 

 

 

 

R1:0

Wait State

3H

 

R1:0 define the minimum number of wait states

 

 

Value

 

 

inserted into the bus cycle.

 

 

 

 

 

 

 

 

 

 

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. U19:16 must be programmed to zero for proper I/O bus cycle operation. Reading this register and the MPCS register (before writing them) enables the PCS chip-selects; however, none of the programmable fields will be properly initialized.

Figure 6-8. PACS Register Definition

6-10

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Intel 80C186XL, 80C188XL user manual PCS Control Register, Pacs, Pcs