CLOCK GENERATION AND POWER MANAGEMENT

X1

 

CLKOUT

 

UCS, LCS

 

MCS3:0

 

PCS6:0,NCS

 

TMR OUT0

 

TMR OUT1

 

HLDA, ALE

 

A19/S6:

 

A16

 

AD15:0

 

S2:0, RD

 

WR, DEN

 

DT/R

 

LOCK

 

RES

 

RESET

 

Minimum RES low

RES high

time 4 CLKOUT

to first bus

periods.

activity 7

 

CLKOUT

 

periods.

 

A1522-0B

Figure 5-7. Warm Reset Waveform

At the second falling CLKOUT edge after sampling RES inactive, the processor deasserts RE- SET. Bus activity starts 6½ CLKOUT periods after recognition of RESin the logic high state. If an alternate bus master asserts HOLD during reset, the processor immediately asserts HLDA and will not prefetch instructions.

5-9

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Image 148
Intel 80C188XL, 80C186XL user manual PCS60,NCS, Clkout