Intel 80C186XL, 80C188XL user manual Rtg, Ext, Alt, Cont

TIMER/COUNTER UNIT

Register Name:

Register Mnemonic:

Register Function:

15

E	I	I	R
N	N	N	I
	H	T	U

Timer 0 and 1 Control Registers

T0CON, T1CON

Defines Timer 0 and 1 operation.

					0
M	R	P	E	A	C
C	T		X	L	O
	G		T	T	N
					T

A1297-0A

Bit	Bit Name	Reset	Function
Mnemonic		State
RTG	Retrigger	X	This bit specifies the action caused by a low-to-high
			transition on the TMR INx input. Set RTG to reset the
			count; clear RTG to enable counting. This bit is
			ignored with external clocking (EXT=1).
P	Prescaler	X	Set to increment the timer when Timer 2 reaches its
			maximum count. Clear to increment the timer at ¼
			CLKOUT. This bit is ignored with external clocking
			(EXT=1).
EXT	External	X	Set to use external clock; clear to use internal clock.
	Clock		The RTG and P bits are ignored with external clocking
			(EXT set).
ALT	Alternate	X	This bit controls whether the timer runs in single or
	Compare		dual maximum count mode (see Figure 9-4 on page
	Register		9-6). Set to specify dual maximum count mode; clear
			to specify single maximum count mode.
CONT	Continuous	X	Set to cause the timer to run continuously. Clear to
	Mode		disable the counter (clear the EN bit) after each
			counting sequence.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 9-5. Timer 0 and Timer 1 Control Registers (Continued)

9-8