Intel 80C188XL, 80C186XL user manual A158 A150, Write Bus Cycle Types, Status Bits Bus Cycle Type

BUS INTERFACE UNIT

			T1				T2			T3	T4
CLKOUT
					Status Valid
		S2:0
		ALE
			A			d
A19:16				ddress Vali				A18:16 = 0, A19=Valid Status
BHE
							Valid
[A15:8]
A15:0
			Address						Data Valid
[AD7:0]				Valid

WR

DT/R

DEN

A1047-0A

				Figure 3-21. Typical Write Bus Cycle
				Table 3-4. Write Bus Cycle Types
	Status Bits			Bus Cycle Type
S2		S1	S0
0		1	0	Write I/O — Initiated by executing IN, OUT, INS, OUTS instructions or by the
				DMA Unit. A15:0 select the desired I/O port. A19:16 are driven to zero (see
				Chapter 10, “Direct Memory Access Unit”).
1		1	0	Write Memory —Initiated by any of the Byte/ Word memory instructions or the
				DMA Unit. A19:0 selects the desired byte or word memory location.

Figure 3-22 illustrates a typical 16-bit interface connection to a read/write device. Write bus cy- cles have many parameters that must be evaluated in determining the compatibility of a memory (or I/O) device. Table 3-5 lists some critical write bus cycle parameters.

3-23