Intel 80C186XL Register Name, DMA Control Register, Register Mnemonic, DxCON, Register Function

DIRECT MEMORY ACCESS UNIT

Register Name:	DMA Control Register
Register Mnemonic:	DxCON
Register Function:	Controls DMA channel parameters.

15

D	D	D	S
M	D	I	M
E	E	N	E
M	C	C	M

SS D I E N C C

TI C N T

S	S	P	I
Y	Y		D
N	N		R
1	0		Q

		0
C	S	W
H	T	O
G	R	R
	T	D

A1180-0A

Bit	Bit Name	Reset			Function
Mnemonic		State
TC	Terminal	X	Set TC to terminate transfers on Terminal Count. This bit
	Count		is ignored for unsynchronized transfers (that is, the DMA
			channel behaves as if TC is set, regardless of its
			condition).
INT	Interrupt	X	Set INT to generate an interrupt request on Terminal
			Count. The TC bit must be set to generate an interrupt.
SYN1:0	Synchron-	XX	Selects channel synchronization:
	ization Type		SYN1 SYN0		Synchronization Type
			0	0	Unsynchronized
			0	1	Source-synchronized
			1	0	Destination-synchronized
			1	1	Reserved (do not use)
P	Relative	X	Set P to select high priority for the channel; clear P to
	Priority		select low priority for the channel.
IDRQ	Internal	X	Set IDRQ to select internal DMA requests and ignore
	DMA		the external DRQ pin. Clear IDRQ to select the DRQ pin
	Request		as the source of DMA requests. When IDRQ is set, the
	Select		channel must be configured for source-synchronized
			transfers (SYN1:0 = 01).

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 10-11. DMA Control Register (Continued)

10-16