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Intel 80C188XL 6.4.3Bus Wait State and Ready Control, CHIP-SELECTUNIT 6.4.2.4PCS Active Range

Models: 80C186XL 80C188XL

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CHIP-SELECT UNIT

CHIP-SELECT UNIT

6.4.2.4PCS Active Range

Each PCS chip-select starts at an offset above the base address programmed in the PACS register and is active for 128 bytes. The base address can start on any 1 Kbyte memory or I/O address location. Table 6-6 lists the active range for each PCS chip-select.

Table 6-6. PCS Active Range

		Chip-		Active Range

		Select		Start Address	Ending Address


				Base	Base + 127 (7FH)
		PCS0

				Base + 128 (080H)	Base + 255 (0FFH)
	PCS1

				Base + 256 (100H)	Base + 383 (17FH)
	PCS2

				Base + 384 (180H)	Base + 511 (1FFH)
	PCS3

				Base + 512 (200H)	Base + 639 (27FH)
	PCS4

				Base + 640 (280H)	Base + 767 (2FFH)
	PCS5

				Base + 768 (300H)	Base + 895 (37FH)
	PCS6

6.4.3Bus Wait State and Ready Control

Normally, the bus ready input must be inactive at the appropriate time to insert wait states into the bus cycle. The Chip-Select Unit can ignore the state of the bus ready input to extend and com- plete the bus cycle automatically. Most memory and peripheral devices operate properly using three or fewer wait states. However, accessing such devices as a dual-port memory, an expansion bus interface, a system bus interface or remote peripheral devices can require more than three wait states to complete a bus cycle.

A three-bit field (R2:0) in the control registers defines the number of wait states and the ready requirements for the chip-selects. Figure 6-11 shows a simplified logic diagram of the wait state and ready control functions.

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Intel 80C188XL 6.4.3Bus Wait State and Ready Control, CHIP-SELECTUNIT 6.4.2.4PCS Active Range, 6.PCS Active Range

Contents

80C186XL/80C188XL Microprocessor User’s Manual 80C186XL/80C188XL Microprocessor User’s Manual 1995Intel Corporation Literature Sales P.O. Box INTRODUCTION CONTENTSCHAPTER CHAPTERBUS INTERFACE UNIT CONTENTSCHAPTER CHAPTER CONTENTSCLOCK GENERATION AND POWER MANAGEMENT PERIPHERAL CONTROL BLOCKREFRESH CONTROL UNIT CONTENTSCHAPTER CHAPTERDIRECT MEMORY ACCESS UNIT CONTENTSTIMER/COUNTER UNIT CHAPTERMATH COPROCESSING CONTENTSCHAPTER ONCE MODE CONTENTSCHAPTER APPENDIX APage FIGURESCONTENTS Page CONTENTSFIGURES 3-15Page CONTENTSFIGURES 6-11Page CONTENTSFIGURES 10-3Page TABLESCONTENTS Page CONTENTSTABLES D-20Example EXAMPLESCONTENTS PageIntroduction Page CHAPTER INTRODUCTION 1.1HOW TO USE THIS MANUAL INTRODUCTIONTable 1-2.Related Documents and Software 1.2RELATED DOCUMENTSINTRODUCTION 1.3.1FaxBack Service 1.3ELECTRONIC SUPPORT SYSTEMS1.3.2Bulletin Board System BBS 1.4TECHNICAL SUPPORT 1.3.3CompuServe Forums1.3.4World Wide Web 1.5PRODUCT LITERATURE 1.6TRAINING CLASSESPage Overview of the 80C186 Family Architecture Page 2.1ARCHITECTURAL OVERVIEW CHAPTER OVERVIEW OF THE 80C186 FAMILYARCHITECTURE 2.1.1Execution Unit OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.1.2Bus Interface Unit Figure 2-3.General Registers 2.1.3General RegistersOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-1.Implicit Use of General Registers 2.1.4Segment RegistersOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Figure 2-4.Segment Registers 2.1.5Instruction PointerOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.6Flags 2.1.7Memory Segmentation Register Function Register NameRegister Mnemonic Reset2.1.8Logical Addresses FFFFFH A B D E G J K 0H Data DS Code CS Stack SS Extra ESB E H J C F HOffset 13H Physical Address Offset 3H Segment Base LogicalAddresses Segment Base 2C4H 2C3H 2C2H 2C1H 2C0H 2BFH 2BEH 2BDH 2BCH 2BBHTable 2-2.Logical Address Sources 2.1.9Dynamically Relocatable CodeOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Before 2.1.10 Stack Implementation 2.1.11 Reserved Memory and I/O SpaceOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Figure 2-10.Stack Operation2.2SOFTWARE OVERVIEW 2.2.1Instruction SetTable 2-3.Data Transfer Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.1Data Transfer Instructions General-PurposeFigure 2-11.Flag Storage Format I = Interrupt Enable Flag T = Trap FlagOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.2Arithmetic InstructionsAddition OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-4.Arithmetic Instructions SubtractionTable 2-6.Bit Manipulation Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.3Bit Manipulation Instructions Bit PatternTable 2-7.String Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.4String Instructions SI DI CX AL/AX DF ZF OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.5Program Transfer Instructions Scan value Destination for LODS Source for STOSUnconditional transfer instructions can transfer control either to a target instruction within the current code segment intrasegment transfer or to a different code segment intersegment trans- fer. The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans- fer FAR. The transfer is made unconditionally when the instruction is executed. CALL, RET and JMP are all unconditional transfers Conditional Transfers OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-9.Program Transfer Instructions Unconditional TransfersCondition Tested OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREMnemonic “Jump if…”2.2.1.6Processor Control Instructions 2.2.2Addressing ModesOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-11.Processor Control InstructionsOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.2.2Memory Addressing ModesEncoded in the Instruction Explicit in the Mod R/M DisplacementOpcode OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREMod R/M DisplacementOpcode BX or BPDisplacement Opcode Mod R/M DisplacementOpcode BX or BPHigh Address Opcode Data Opcode SI DISource EA Destination EA Port Address Direct Port AddressingType OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-12.Supported Data Types DescriptionOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Interrupt Control Unit NMI CPUMaskable Interrupt Request Interrupt Acknowledge External Interrupt SourcesOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Figure 2-25.Interrupt Vector Table3.The current CS and IP are pushed onto the stack Stack PSW OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Divide Error — TypeSingle Step — Type 2.3.1.2Maskable InterruptsInterrupt on Overflow — Type Numerics Coprocessor Fault — TypeBreakpoint Interrupt — Type Array Bounds Check — Type2.3.2Software Interrupts 2.3.3Interrupt LatencyTotal 2.3.4Interrupt Response TimeClocks 2.3.5Interrupt and Exception PriorityService Routine IRET Execute Divide Divide ErrorPush PSW, CS, IP Fetch Divide Error Vector Service Routine IRETNMI Instruction Push PSW, CS, IP Fetch Divide Error VectorService Routine IRET Trap Flag = ??? Trap Flag =Interrupt Enable Bit IE = Trap Flag TF = Page Bus Interface Unit Page 3.2ADDRESS AND DATA BUS CONCEPTS CHAPTER BUS INTERFACE UNIT3.1MULTIPLEXED ADDRESS AND DATA BUS 3.2.116-BitData Bus512 KBytes 1 MByte512 KBytes Even Byte Transfer Odd Byte TransferD7:0 A0 Low A19D15 8 BHE BUS INTERFACE UNIT3.2.28-BitData Bus First Bus CycleSecond Bus Cycle 3.3MEMORY AND I/O INTERFACES A19:0D7:0 First Bus Cycle3.4BUS CYCLE OPERATION 3.3.116-BitBus Memory and I/O Requirements3.3.28-BitBus Memory and I/O Requirements Falling PhaseCLKOUT RisingBus Ready 3.4.1Address/Status Phase or TI Signals From CPU 3.4.2Data Phase 3.4.3Wait Statesor TW T1 T2 T3 TW TW T4 CLKOUT Clear Clock CS1 CS2 CS3 CS4 ALE CLKOUTWait State Module Input Input READYREADY Wait State Module CS1 Enable CS2Load CLKOUTARDY SRDY 3.4.4Idle StatesCLKOUT •The instruction prefetch queue is full BUS INTERFACE UNIT 3.5BUS CYCLES3.5.1Read Bus Cycles Table 3-2. Read Bus Cycle TypesCLKOUT 27C256 27C2563.5.2Write Bus Cycles CLKOUT AD7:0 AD15:8 LA15:1 RD LA0 WR BHEA0:14 OE I/O1:8 WE CS1 A0:14 OE I/O1:8 WE BUS INTERFACE UNITTable 3-5.Write Cycle Critical Timing Parameters 3.5.3Interrupt Acknowledge Bus CycleBUS INTERFACE UNIT T1 T2 CLKOUT ALE S2:0 INTA0 INTA1 AD15:0 AD7:0 LOCKDT/R DEN A19:16 A15:8 BHE RD, WR T3 T4Processor 3.5.4HALT Bus Cycle CLKOUT CONTROL 3.5.5Temporarily Exiting the HALT Bus StateCLKOUT HOLD HLDA AD15:0 AD7:0 A15:8 A19:16 BUS INTERFACE UNIT CLKOUT ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHERFSH 3.5.6Exiting HALT NMI/INTx ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHE 3.6SYSTEM DESIGN ALTERNATIVESCLKOUT RFSH3.6.1Buffering the Data Bus A19:16 3.6.2Synchronizing Software and Hardware Events 3.6.3Using a Locked Bus BUS INTERFACE UNIT 3.6.4Using the Queue Status SignalsTable 3-7.Queue Status Signal Decoding BUS INTERFACE UNIT 3.7MULTI-MASTERBUS SYSTEM DESIGNS3.7.1Entering Bus HOLD Figure 3-33.Queue Status TimingCLKOUT BUS INTERFACE UNIT 3.7.1.2Refresh Operation During a Bus HOLDCLKOUT PRE DQ CLR 3.7.2Exiting HOLD+5 HLDA RESET HOLD Latched HLDA3.8BUS CYCLE PRIORITIES 9.DMA bus cycles Page Peripheral Control Block Page 4.2PCB RELOCATION REGISTER CHAPTER PERIPHERAL CONTROL BLOCK4.1PERIPHERAL CONTROL REGISTERS Relocates the PCB within memory or I/O space PCB Relocation RegisterRELREG Register NameFunction PERIPHERAL CONTROL BLOCKTable 4-1.Peripheral Control Block Function4.3RESERVED LOCATIONS 4.4ACCESSING THE PERIPHERAL CONTROL BLOCK4.4.2READY Signals and Wait States 4.4.1Bus Cyclesaddress 4.4.3F-BusOperationWord reads Byte reads4.4.3.3Accessing Reserved Locations 4.5SETTING THE PCB BASE LOCATION4.4.3.2Accessing the Peripheral Control Registers PERIPHERAL CONTROL BLOCKPage Page Clock Generation and Power Management Page 5.1.1Crystal Oscillator CHAPTER CLOCK GENERATION AND POWER MANAGEMENT5.1CLOCK GENERATION 180˚ CLOCK GENERATION AND POWER MANAGEMENTZ0 = Inverter Output Z 5.1.1.1Oscillator OperationFundamental CLKOUT CLOCK GENERATION AND POWER MANAGEMENTFigure 5-4.Equations for Crystal Calculations Third-OvertoneCrystalCLOCK GENERATION AND POWER MANAGEMENT 5.1.1.2Selecting Crystals5.1.3Output from the Clock Generator 5.1.2Using an External Oscillator5.1.4Reset and Clock Synchronization Figure 5-5.Simple RC Circuit for Powerup Reset RESET IN 1µf typicalCLOCK GENERATION AND POWER MANAGEMENT 50 k typicalFigure 5-6.Cold Reset Waveform CLOCK GENERATION AND POWER MANAGEMENTRESET X1 VccCLOCK GENERATION AND POWER MANAGEMENT Figure 5-7.Warm Reset Waveform5.2POWER MANAGEMENT 5.2.1.1Entering Power-SaveMode 5.2.1Power-SaveModeCLOCK GENERATION AND POWER MANAGEMENT Enables and sets clock division factor 0 F F 1 Register Name Register Mnemonic Register FunctionPower Save Register PWRSAV CLOCK GENERATION AND POWER MANAGEMENTFigure 5-10. Power-SaveClock Transition CLKOUT WRCLOCK GENERATION AND POWER MANAGEMENT 5.2.1.2Leaving Power-SaveModeCLOCK GENERATION AND POWER MANAGEMENT Chip-SelectUnit Page 6.1COMMON METHODS FOR GENERATING CHIP-SELECTS 6.2CHIP-SELECTUNIT FEATURES AND BENEFITSCHAPTER CHIP-SELECTUNIT Chip-SelectsUsing 6.3CHIP-SELECTUNIT FUNCTIONAL OVERVIEWChip-SelectsUsing CHIP-SELECTUNITInternal device EPROM or Flash memory types 1.The chip-selectis enabled 6.4PROGRAMMING 6.4.1Initialization SequenceRegister Function Register NameRegister Mnemonic CHIP-SELECTUNITRegister Function Register NameRegister Mnemonic CHIP-SELECTUNITRegister Function Register NameRegister Mnemonic CHIP-SELECTUNITRegister Function Register NameRegister Mnemonic CHIP-SELECTUNITCHIP-SELECTUNIT MPCSRegister Mnemonic Figure 6-9.MPCS Register Definition6.4.2Programming the Active Ranges 6.4.2.3MCS Active Range Table 6.3 LCS Active RangeCHIP-SELECTUNIT 6.4.2.2LCS Active Range Table 6-4.MCS Active RangeStarting Address Table 6-6.PCS Active Range 6.4.3Bus Wait State and Ready ControlCHIP-SELECTUNIT 6.4.2.4PCS Active Range Wait State Value R1:0 State Counter 6.4.4Overlapping Chip-SelectsBUS READY R2 Control Bit Wait READY Wait State Ready6.4.5Memory or I/O Bus Cycle Decoding 6.4.6Programming ConsiderationsExternal Master Chip Select 6.6.1Example 1: Typical System ConfigurationCSU Chip Select Device select 6.5CHIP-SELECTSAND BUS HOLDCHIP-SELECTUNIT Figure 6-13.Typical SystemCHIP-SELECTUNIT Example 6-1.Initializing the Chip-SelectUnitCHIP-SELECTUNIT CHIP-SELECTUNIT Place memory variables hereRefresh Control Unit Page CHAPTER REFRESH CONTROL UNIT 7.3REFRESH CONTROL UNIT OPERATION 7.1THE ROLE OF THE REFRESH CONTROL UNIT7.2REFRESH CONTROL UNIT CAPABILITIES Refresh Control Unit Operation Set E Bit Figure 7-3.Refresh Address Formation 7.4REFRESH ADDRESSESREFRESH CONTROL UNIT REFRESH CONTROL UNIT 7.5REFRESH BUS CYCLES7.6GUIDELINES FOR DESIGNING DRAM CONTROLLERS Table 7-1.Identification of Refresh Bus CyclesT3/TW 7.7.2Refresh Control Unit Registers 7.7PROGRAMMING THE REFRESH CONTROL UNIT7.7.1Calculating the Refresh Interval REFRESH CONTROL UNITRegister Mnemonic RFBASERegister Name:Refresh Base Address Register Sets refresh rate Refresh Clock Interval RegisterRFTIME Register NameRefresh Control Register RFCON 7.7.3Programming ExampleRegister Name Register Mnemonic Register Function Controls Refresh Unit operationREFRESH CONTROL UNIT Example 7-1.Initializing the Refresh Control Unit7.8REFRESH OPERATION AND BUS HOLD REFRESH CONTROL UNITCLKOUT Page Interrupt Control Unit Page CHAPTER INTERRUPT CONTROL UNIT 8.1FUNCTIONAL OVERVIEW8.2MASTER MODE 8.2.1Generic Functions in Master Mode8.2.1.2Interrupt Priority Table 8-1.Default Interrupt PrioritiesINTERRUPT CONTROL UNIT 8.2.1.1Interrupt Masking Interrupt NameINTERRUPT CONTROL UNIT 8.2.1.3Interrupt Nesting8.3.1Typical Interrupt Sequence 8.3.2Priority Resolution8.3FUNCTIONAL OPERATION IN MASTER MODE •the Interrupt Control Unit has been initialized 8.3.2.2Interrupts That Share a Single Source 8.3.3Cascading with External 8259AsINTERRUPT CONTROL UNIT INT0 INTERRUPT CONTROL UNIT 8.3.4Interrupt Acknowledge Sequence8.3.5Polling Table 8-2.Fixed Interrupt Types8.3.6Edge and Level Triggering 8.3.7Additional Latency and Response Time8.4PROGRAMMING THE INTERRUPT CONTROL UNIT 8.4.1Interrupt Control Registers INTERRUPT CONTROL UNITRegister Mnemonic: TCUCON, DMA0CON, DMA1CON I2CON, I3CON Register MnemonicINTERRUPT CONTROL UNIT I0CON, I1CONRegister Mnemonic REQST 8.4.2Interrupt Request RegisterInterrupt Request Register Stores pending interrupt requestsMasks individual interrupt sources Interrupt Mask RegisterIMASK 8.4.4Priority Mask RegisterPriority Mask Register 8.4.5In-ServiceRegisterRegister Name Register MnemonicRegister Name 8.4.6Poll and Poll Status RegistersFigure 8-10. In-ServiceRegister Register MnemonicINTERRUPT CONTROL UNIT Register Name Register Mnemonic Register FunctionPoll Register POLL Figure 8-11.Poll RegisterRegister Name Register Mnemonic Register Function 8.4.7End-of-InterruptEOI RegisterRead to check for pending interrupts when polling Poll Status Register POLLSTSRegister Name Register Mnemonic Register Function 8.4.8Interrupt Status RegisterUsed to issue an EOI command End-of-InterruptRegister EOIInterrupt Status Register INTSTS 8.5SLAVE MODERegister Name Register Mnemonic Register Function 82C59A INT0 INTA 80186 Modular Core Select IRQ8259A INTA8.5.1Slave Mode Programming Table 8-5.Slave Mode Fixed Interrupt Type Bits INTERRUPT CONTROL UNIT8.5.1.1Interrupt Vector Register INTERRUPT CONTROL UNIT INTVECRegister Mnemonic 8.5.1.2End-Of-InterruptRegisterEnd-of-InterruptRegister in Slave Mode Used to issue the EOI commandRegister Name Register Mnemonic8.5.2Interrupt Vectoring in Slave Mode Interrupt presented to Interrupt Control Unit INTERRUPT CONTROL UNIT Page Timer/Counter Unit Page CHAPTER TIMER/COUNTER UNIT 9.1FUNCTIONAL OVERVIEWT0 In T1IN T0OUT T1OUT TIMER/COUNTER UNITT0IN TIMER/COUNTER UNIT Figure 9-3.Timers 0 and 1 Flow ChartTIMER/COUNTER UNIT Figure 9-3.Timers 0 and 1 Flow Chart ContinuedMaxcount B 9.2PROGRAMMING THE TIMER/COUNTER UNITMaxcount A Dual Maximum Count ModeTIMER/COUNTER UNIT Timer 0 and 1 Control Registers T0CON, T1CONDefines Timer 0 and 1 operation Figure 9-5.Timer 0 and Timer 1 Control RegistersTIMER/COUNTER UNIT Register Name Register Mnemonic Register FunctionTIMER/COUNTER UNIT Timer 2 Control Register T2CONDefines Timer 2 operation Figure 9-6.Timer 2 Control RegisterT0CNT, T1CNT, T2CNT Timer Count RegisterContains the current timer count TIMER/COUNTER UNIT9.2.1Initialization Sequence TIMER/COUNTER UNIT 9.2.2Clock Sources9.2.3Counting Modes Table 9-1.Timer 0 and 1 Clock SourcesTIMER/COUNTER UNIT 9.2.3.1RetriggeringTable 9-2.Timer Retriggering 9.2.4Pulsed and Variable Duty Cycle OutputTIMER/COUNTER UNIT Internal Count Value 9.2.5Enabling/Disabling CountersTimer Serviced 1 Maxcount -9.2.7Programming Considerations 9.2.6Timer Interrupts9.3.1Input Setup and Hold Timings 9.3TIMING9.3.4Square-WaveGenerator 9.3.2Synchronization and Maximum Frequency9.3.3Real-TimeClock 9.3.5Digital One-ShotTIMER/COUNTER UNIT Example 9-1.Configuring a Real-TimeClockTIMER/COUNTER UNIT TIMER/COUNTER UNIT enable interruptsTIMER/COUNTER UNIT Example 9-2.Configuring a Square-WaveGeneratorTIMER/COUNTER UNIT Example 9-3.Configuring a Digital One-ShotTIMER/COUNTER UNIT Page Direct Memory Access Unit Page 10.1.1 The DMA Transfer CHAPTER DIRECT MEMORY ACCESS UNIT10.1 FUNCTIONAL OVERVIEW Fetch 10.1.2 Source and Destination Pointers 10.1.3 DMA Requests10.1.4 External Requests Fetch Cycle 10.1.5.1Timer 2-InitiatedTransfers 10.1.5 Internal Requests10.1.7.1Termination at Terminal Count 10.1.6 DMA Transfer CountsDIRECT MEMORY ACCESS UNIT 10.1.7.2Software Termination10.1.10 The Two-ChannelDMA Unit 10.1.8 DMA Unit Interrupts10.1.9 DMA Cycles and the BIU Module 10.2 PROGRAMMING THE DMA UNIT 10.2.1 DMA Channel ParametersRegister Mnemonic DxSRCHRegister Name:DMA Source Address Pointer High Register Mnemonic DxSRCLRegister Name:DMA Source Address Pointer Low DxDSTH DIRECT MEMORY ACCESS UNITRegister Mnemonic Register FunctionRegister Mnemonic DxDSTLRegister Name:DMA Destination Address Pointer Low Controls DMA channel parameters DMA Control RegisterDxCON DIRECT MEMORY ACCESS UNITDMA Control Register DIRECT MEMORY ACCESS UNITRegister Name Register MnemonicRegister Mnemonic Register NameDMA Control Register DxCON10.2.1.5Selecting Channel Synchronization DIRECT MEMORY ACCESS UNIT10.2.1.4Arming the DMA Channel 10.2.1.6Programming the Transfer Count OptionsContains the DMA channel’s transfer count DMA Transfer CountDxTC Register Name10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT 10.2.2 Suspension of DMA Transfers10.2.3 Initializing the DMA Unit 10.3.1 DRQ Pin Timing Requirements10.3.2 DMA Latency 10.3.3 DMA Transfer Rates10.3.4 Generating a DMA Acknowledge 10.4 DMA UNIT EXAMPLESDIRECT MEMORY ACCESS UNIT Example 10-1.Initializing the DMA UnitDIRECT MEMORY ACCESS UNIT Example 10-1.Initializing the DMA Unit ContinuedSECTORS DIRECT MEMORY ACCESS UNITExample 10-1.Initializing the DMA Unit Continued DIRECT MEMORY ACCESS UNIT Example 10-2.Timed DMA TransfersDIRECT MEMORY ACCESS UNIT Example 10-2.Timed DMA Transfers ContinuedPage Math Coprocessing Page 11.2 AVAILABILITY OF MATH COPROCESSING CHAPTER MATH COPROCESSING11.1 OVERVIEW OF MATH COPROCESSING 11.3 THE 80C187 MATH COPROCESSOR 11.3.1 80C187 Instruction Set•the 80C187 uses register or memory operands Addition MATH COPROCESSINGTable 11-2.80C187 Arithmetic Instructions Division11.3.1.4Transcendental Instructions MATH COPROCESSING 11.3.1.3Comparison InstructionsTable 11-3.80C187 Comparison Instructions Table 11-4.80C187 Transcendental Instructions11.3.1.6Processor Control Instructions MATH COPROCESSING 11.3.1.5Constant InstructionsTable 11-5.80C187 Constant Instructions Table 11-6.80C187 Processor Control Instructions11.3.2 80C187 Data Types 11.4 MICROPROCESSOR AND COPROCESSOR OPERATIONMATH COPROCESSING Figure 11-1. 80C187-SupportedData TypesModular MATH COPROCESSING80C187 CoreMATH COPROCESSING 11.4.2 Processor Bus Cycles Accessing the 80C18711.4.1 Clocking the 80C187 Table 11-7.80C187 I/O Port Assignments11.4.3 System Design Tips Modular MATH COPROCESSING80C187 Core11.4.4 Exception Trapping 11.5 EXAMPLE MATH COPROCESSOR ROUTINESModular Core MATH COPROCESSING80C186 80C187MATH COPROCESSING MATH COPROCESSING ONCE Mode Page CHAPTER ONCE MODE 12.1 ENTERING/LEAVING ONCE MODEFigure 12-1.Entering/Leaving ONCE Mode bidirectional weakly held pins except OSCOUTONCE MODE All output80C186 Instruction Set Additions and Extensions Page PUSHA/POPA A.1 80C186 INSTRUCTION SET ADDITIONSA.1.1 Data Transfer Instructions OUTS port, destination_string A.1.2 String InstructionsINS source_string, port A.1.3 High-LevelInstructions1.Main has variables at fixed locations Figure A-3.Stack Frame for Main at Level Figure A-2.Variable Access in Nested Procedures80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS BPA = BP Value for Procedure AFigure A-4.Stack Frame for Procedure A at Level BP SPOld BP BPM BPM BPM BPA BPA BPM BPA BPB 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSBP SP Display B Dynamic Storage BLEAVE 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSA.2.1 Data Transfer Instructions BOUND register, addressA.2 80C186 INSTRUCTION SET ENHANCEMENTS PUSH dataA.2.3 Bit Manipulation Instructions A.2.2 Arithmetic InstructionsIMUL destination, source, data SAL destination, countRCL destination, count ROL destination, countROR destination, count RCR destination, countInput Synchronization Page B.1 WHY SYNCHRONIZERS ARE REQUIRED APPENDIX B INPUT SYNCHRONIZATIONB.2 ASYNCHRONOUS PINS Instruction Set Descriptions Page APPENDIX C INSTRUCTION SET DESCRIPTIONS Table C-1.Instruction Format VariablesOperand INSTRUCTION SET DESCRIPTIONSTable C-2.Instruction Operands DescriptionINSTRUCTION SET DESCRIPTIONS Table C-3.Flag Bit FunctionsINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction SetADC dest, src INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued DescriptionINSTRUCTION SET DESCRIPTIONS Call ProcedureCALL procedure-name Table C-4.Instruction Set ContinuedINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedTable C-4.Instruction Set Continued Clear Interrupt-enableFlagINSTRUCTION SET DESCRIPTIONS NameC-10 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-11 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-12 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameINSTRUCTION SET DESCRIPTIONS When Source Operand is a ByteWhen Source Operand is a Word Table C-4.Instruction Set ContinuedTable C-4.Instruction Set Continued Procedure EntryINSTRUCTION SET DESCRIPTIONS C-14C-15 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameINSTRUCTION SET DESCRIPTIONS When Source Operand is a ByteWhen Source Operand is a Word Table C-4.Instruction Set ContinuedC-17 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued IN accum, portC-18 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-19 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-20 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JA disp8JAE disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JNB disp8JE disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JZ disp8JL disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JGE disp8JNE disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JNZ disp8JO disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JP disp8C-26 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued LDS dest, srcTable C-4.Instruction Set Continued Load Pointer Using ESINSTRUCTION SET DESCRIPTIONS C-27C-28 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued LODS src-stringC-29 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued MOV dest, srcC-30 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued MOVS dest-string, src-stringC-31 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-32 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-33 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-34 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-35 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-36 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-37 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-38 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-39 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameSHL dest, count INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued SAL dest, countC-41 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameINSTRUCTION SET DESCRIPTIONS When Source Operand is a ByteWhen Source Operand is a Word Table C-4.Instruction Set ContinuedC-43 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued SHR dest, srcC-44 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued STOS dest-stringC-45 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-46 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-47 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NamePage Instruction Set Opcodes and Clock Cycles Page Table D-1.Operand Variables APPENDIX D INSTRUCTION SET OPCODESAND CLOCK CYCLES Function INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary FormatDATA TRANSFER INSTRUCTIONS Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued ARITHMETIC INSTRUCTIONSARITHMETIC INSTRUCTIONS Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued ARITHMETIC INSTRUCTIONS Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued BIT MANIPULATION INSTRUCTIONSBIT MANIPULATION INSTRUCTIONS Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued Shifts/RotatesINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedPROGRAM TRANSFER INSTRUCTIONS Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued Iteration ControlTable D-3.Machine Instruction Decoding Guide INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued ByteByte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte BytesByte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4.Mnemonic Encoding Matrix Left HalfD-21 INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-4.Mnemonic Encoding Matrix Right Half Definition INSTRUCTION SET OPCODES AND CLOCK CYCLESAbbr AbbrIndex Page INDEX ARDY, See READY ArithmeticData bus, See Address and data bus INDEXCrystal‚ See Oscillator See also Refresh Control Unit INDEXSee also Bus cycles Index-3interrupt INDEXIndex-4 INDEX Index-5INDEX Index-6Index-7 Timers‚ See Timer Counter Unit TCUINDEX INDEX Index-8