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Intel 80C188XL, 80C186XL user manual System Design Tips

Models: 80C186XL 80C188XL

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11.4.3 System Design Tips

MATH COPROCESSING

Bus cycles involving the 80C187 Math Coprocessor behave exactly like other I/O bus cycles with respect to the processor’s control pins. See “System Design Tips” for information on integrating the 80C187 into the overall system.

11.4.3 System Design Tips

All 80C187 operations require that bus ready be asserted. The simplest way to return the ready indication is through hardware connected to the processor’s external ready pin. If you program a chip-select to cover the math coprocessor port addresses, its ready programming is in force and can provide bus ready for coprocessor accesses. The user must verify that there are no conflicts from other hardware connected to that chip-select pin.

A chip-select pin goes active on 80C187 accesses if you program it for a range including the math coprocessor I/O ports. The converse is not true — a non-80C187 access cannot activate N CS (nu- merics coprocessor select), regardless of programming.

In a buffered system, it is customary to place the 80C187 on the local bus. Since DTR and DEN function normally during 80C187 transfers, you must qualify DEN with NCS (see Figure 11-3). Otherwise, contention between the 80C187 and the transceivers occurs on read cycles to the 80C187.

The microprocessor’s local bus is available to the integrated peripherals during numerics execu- tion whenever the CPU is not communicating with the 80C187. The idle bus allows the processor to intersperse DRAM refresh cycles and DMA cycles with accesses to the 80C187.

The microprocessor’s local bus is available to alternate bus masters during execution of numerics instructions when the CPU does not need it. Bus cycles driven by alternate masters (via the HOLD/HLDA protocol) can suspend coprocessor bus cycles for an indefinite period.

The programmer can lock 80C187 instructions. The CPU asserts the LOCK pin for the entire du- ration of a numerics instruction, monopolizing the bus for a very long time.

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Intel 80C188XL, 80C186XL user manual System Design Tips

Contents

80C186XL/80C188XL Microprocessor User’s Manual 80C186XL/80C188XL Microprocessor User’s Manual 1995Intel Corporation Literature Sales P.O. Box CONTENTS CHAPTERINTRODUCTION CHAPTERBUS INTERFACE UNIT CONTENTSCHAPTER CONTENTS CLOCK GENERATION AND POWER MANAGEMENTCHAPTER PERIPHERAL CONTROL BLOCKCONTENTS CHAPTERREFRESH CONTROL UNIT CHAPTERCONTENTS TIMER/COUNTER UNITDIRECT MEMORY ACCESS UNIT CHAPTERMATH COPROCESSING CONTENTSCHAPTER CONTENTS ONCE MODECHAPTER APPENDIX AFIGURES CONTENTSFigure PageCONTENTS FIGURESFigure PageCONTENTS FIGURESFigure PageCONTENTS FIGURESFigure PageTABLES CONTENTSTable PageCONTENTS TABLESTable PageEXAMPLES CONTENTSExample PageIntroduction Page CHAPTER INTRODUCTION 1.1HOW TO USE THIS MANUAL INTRODUCTIONTable 1-2.Related Documents and Software 1.2RELATED DOCUMENTSINTRODUCTION 1.3.1FaxBack Service 1.3ELECTRONIC SUPPORT SYSTEMS1.3.2Bulletin Board System BBS 1.4TECHNICAL SUPPORT 1.3.3CompuServe Forums1.3.4World Wide Web 1.5PRODUCT LITERATURE 1.6TRAINING CLASSESPage Overview of the 80C186 Family Architecture Page 2.1ARCHITECTURAL OVERVIEW CHAPTER OVERVIEW OF THE 80C186 FAMILYARCHITECTURE 2.1.1Execution Unit OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.1.2Bus Interface Unit Figure 2-3.General Registers 2.1.3General RegistersOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-1.Implicit Use of General Registers 2.1.4Segment RegistersOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Figure 2-4.Segment Registers 2.1.5Instruction PointerOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.6Flags 2.1.7Memory Segmentation Register Name Register MnemonicRegister Function Reset2.1.8Logical Addresses Data: DS Code: CS Stack: SS Extra: ES B E H JFFFFFH A B D E G J K 0H C F H IPhysical Address Offset 3H Segment Base Logical Addresses Segment BaseOffset 13H 2C4H 2C3H 2C2H 2C1H 2C0H 2BFH 2BEH 2BDH 2BCH 2BBHTable 2-2.Logical Address Sources 2.1.9Dynamically Relocatable CodeOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Before 2.1.10 Stack Implementation 2.1.11 Reserved Memory and I/O SpaceOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Figure 2-10.Stack Operation2.2SOFTWARE OVERVIEW 2.2.1Instruction SetOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.1Data Transfer InstructionsTable 2-3.Data Transfer Instructions General-PurposeI = Interrupt Enable Flag T = Trap Flag OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-11.Flag Storage Format 2.2.1.2Arithmetic InstructionsOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-4.Arithmetic InstructionsAddition SubtractionOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.3Bit Manipulation InstructionsTable 2-6.Bit Manipulation Instructions Bit PatternTable 2-7.String Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.4String Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.5Program Transfer InstructionsSI DI CX AL/AX DF ZF Scan value Destination for LODS Source for STOSUnconditional transfer instructions can transfer control either to a target instruction within the current code segment intrasegment transfer or to a different code segment intersegment trans- fer. The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans- fer FAR. The transfer is made unconditionally when the instruction is executed. CALL, RET and JMP are all unconditional transfers OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-9.Program Transfer InstructionsConditional Transfers Unconditional TransfersOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE MnemonicCondition Tested “Jump if…”2.2.2Addressing Modes OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.6Processor Control Instructions Table 2-11.Processor Control InstructionsOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.2.2Memory Addressing ModesEncoded in the Instruction Explicit in the Displacement OpcodeMod R/M OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREDisplacement OpcodeMod R/M BX or BPDisplacement Opcode Displacement OpcodeMod R/M BX or BPHigh Address Opcode SI DI Source EA Destination EAOpcode Data Port Address Direct Port AddressingOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-12.Supported Data TypesType DescriptionOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE NMI CPU Maskable Interrupt Request Interrupt AcknowledgeInterrupt Control Unit External Interrupt SourcesOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Figure 2-25.Interrupt Vector Table3.The current CS and IP are pushed onto the stack Stack PSW Divide Error — Type Single Step — TypeOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.3.1.2Maskable InterruptsNumerics Coprocessor Fault — Type Breakpoint Interrupt — TypeInterrupt on Overflow — Type Array Bounds Check — Type2.3.2Software Interrupts 2.3.3Interrupt Latency2.3.4Interrupt Response Time ClocksTotal 2.3.5Interrupt and Exception PriorityDivide Error Push PSW, CS, IP Fetch Divide Error VectorService Routine IRET Execute Divide Service Routine IRETPush PSW, CS, IP Fetch Divide Error Vector Service Routine IRET Trap Flag = ???NMI Instruction Trap Flag =Interrupt Enable Bit IE = Trap Flag TF = Page Bus Interface Unit Page CHAPTER BUS INTERFACE UNIT 3.1MULTIPLEXED ADDRESS AND DATA BUS3.2ADDRESS AND DATA BUS CONCEPTS 3.2.116-BitData Bus512 KBytes 1 MByte512 KBytes Even Byte Transfer Odd Byte TransferA19:1 D15:8 BHED7:0 A0 Low BUS INTERFACE UNIT3.2.28-BitData Bus First Bus CycleSecond Bus Cycle A19:0 D7:03.3MEMORY AND I/O INTERFACES First Bus Cycle3.4BUS CYCLE OPERATION 3.3.116-BitBus Memory and I/O Requirements3.3.28-BitBus Memory and I/O Requirements Phase CLKOUTFalling RisingBus Ready 3.4.1Address/Status Phase or TI Signals From CPU 3.4.2Data Phase 3.4.3Wait Statesor TW T1 T2 T3 TW TW T4 CLKOUT CS1 CS2 CS3 CS4 ALE CLKOUT Wait State Module Input InputClear Clock READYWait State Module CS1 Enable CS2 LoadREADY CLKOUTARDY SRDY 3.4.4Idle StatesCLKOUT •The instruction prefetch queue is full 3.5BUS CYCLES 3.5.1Read Bus CyclesBUS INTERFACE UNIT Table 3-2. Read Bus Cycle TypesCLKOUT 27C256 27C2563.5.2Write Bus Cycles CLKOUT LA15:1 RD LA0 WR BHE A0:14 OE I/O1:8 WE CS1 A0:14 OE I/O1:8 WEAD7:0 AD15:8 BUS INTERFACE UNITTable 3-5.Write Cycle Critical Timing Parameters 3.5.3Interrupt Acknowledge Bus CycleBUS INTERFACE UNIT CLKOUT ALE S2:0 INTA0 INTA1 AD15:0 AD7:0 LOCK DT/R DEN A19:16 A15:8 BHE RD, WRT1 T2 T3 T4Processor 3.5.4HALT Bus Cycle CLKOUT CONTROL 3.5.5Temporarily Exiting the HALT Bus StateCLKOUT HOLD HLDA AD15:0 AD7:0 A15:8 A19:16 BUS INTERFACE UNIT CLKOUT ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHERFSH 3.5.6Exiting HALT 3.6SYSTEM DESIGN ALTERNATIVES CLKOUTNMI/INTx ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHE RFSH3.6.1Buffering the Data Bus A19:16 3.6.2Synchronizing Software and Hardware Events 3.6.3Using a Locked Bus BUS INTERFACE UNIT 3.6.4Using the Queue Status SignalsTable 3-7.Queue Status Signal Decoding 3.7MULTI-MASTERBUS SYSTEM DESIGNS 3.7.1Entering Bus HOLDBUS INTERFACE UNIT Figure 3-33.Queue Status TimingCLKOUT BUS INTERFACE UNIT 3.7.1.2Refresh Operation During a Bus HOLDCLKOUT 3.7.2Exiting HOLD +5 HLDA RESET HOLDPRE DQ CLR Latched HLDA3.8BUS CYCLE PRIORITIES 9.DMA bus cycles Page Peripheral Control Block Page 4.2PCB RELOCATION REGISTER CHAPTER PERIPHERAL CONTROL BLOCK4.1PERIPHERAL CONTROL REGISTERS PCB Relocation Register RELREGRelocates the PCB within memory or I/O space Register NamePERIPHERAL CONTROL BLOCK Table 4-1.Peripheral Control BlockFunction Function4.4ACCESSING THE PERIPHERAL CONTROL BLOCK 4.4.2READY Signals and Wait States4.3RESERVED LOCATIONS 4.4.1Bus Cycles4.4.3F-BusOperation Word readsaddress Byte reads4.5SETTING THE PCB BASE LOCATION 4.4.3.2Accessing the Peripheral Control Registers4.4.3.3Accessing Reserved Locations PERIPHERAL CONTROL BLOCKPage Page Clock Generation and Power Management Page 5.1.1Crystal Oscillator CHAPTER CLOCK GENERATION AND POWER MANAGEMENT5.1CLOCK GENERATION CLOCK GENERATION AND POWER MANAGEMENT Z0 = Inverter Output Z180˚ 5.1.1.1Oscillator OperationFundamental CLOCK GENERATION AND POWER MANAGEMENT Figure 5-4.Equations for Crystal CalculationsCLKOUT Third-OvertoneCrystalCLOCK GENERATION AND POWER MANAGEMENT 5.1.1.2Selecting Crystals5.1.3Output from the Clock Generator 5.1.2Using an External Oscillator5.1.4Reset and Clock Synchronization RESET IN 1µf typical CLOCK GENERATION AND POWER MANAGEMENTFigure 5-5.Simple RC Circuit for Powerup Reset 50 k typicalCLOCK GENERATION AND POWER MANAGEMENT RESETFigure 5-6.Cold Reset Waveform X1 VccCLOCK GENERATION AND POWER MANAGEMENT Figure 5-7.Warm Reset Waveform5.2POWER MANAGEMENT 5.2.1.1Entering Power-SaveMode 5.2.1Power-SaveModeCLOCK GENERATION AND POWER MANAGEMENT Register Name Register Mnemonic Register Function Power Save Register PWRSAVEnables and sets clock division factor 0 F F 1 CLOCK GENERATION AND POWER MANAGEMENTCLKOUT WR CLOCK GENERATION AND POWER MANAGEMENTFigure 5-10. Power-SaveClock Transition 5.2.1.2Leaving Power-SaveModeCLOCK GENERATION AND POWER MANAGEMENT Chip-SelectUnit Page 6.1COMMON METHODS FOR GENERATING CHIP-SELECTS 6.2CHIP-SELECTUNIT FEATURES AND BENEFITSCHAPTER CHIP-SELECTUNIT 6.3CHIP-SELECTUNIT FUNCTIONAL OVERVIEW Chip-SelectsUsingChip-SelectsUsing CHIP-SELECTUNITInternal device EPROM or Flash memory types 1.The chip-selectis enabled 6.4PROGRAMMING 6.4.1Initialization SequenceRegister Name Register MnemonicRegister Function CHIP-SELECTUNITRegister Name Register MnemonicRegister Function CHIP-SELECTUNITRegister Name Register MnemonicRegister Function CHIP-SELECTUNITRegister Name Register MnemonicRegister Function CHIP-SELECTUNITMPCS Register MnemonicCHIP-SELECTUNIT Figure 6-9.MPCS Register Definition6.4.2Programming the Active Ranges Table 6.3 LCS Active Range CHIP-SELECTUNIT 6.4.2.2LCS Active Range6.4.2.3MCS Active Range Table 6-4.MCS Active RangeStarting Address Table 6-6.PCS Active Range 6.4.3Bus Wait State and Ready ControlCHIP-SELECTUNIT 6.4.2.4PCS Active Range 6.4.4Overlapping Chip-Selects BUS READY R2 Control Bit WaitWait State Value R1:0 State Counter READY Wait State Ready6.4.5Memory or I/O Bus Cycle Decoding 6.4.6Programming Considerations6.6.1Example 1: Typical System Configuration CSU Chip Select Device selectExternal Master Chip Select 6.5CHIP-SELECTSAND BUS HOLDCHIP-SELECTUNIT Figure 6-13.Typical SystemCHIP-SELECTUNIT Example 6-1.Initializing the Chip-SelectUnitCHIP-SELECTUNIT CHIP-SELECTUNIT Place memory variables hereRefresh Control Unit Page CHAPTER REFRESH CONTROL UNIT 7.3REFRESH CONTROL UNIT OPERATION 7.1THE ROLE OF THE REFRESH CONTROL UNIT7.2REFRESH CONTROL UNIT CAPABILITIES Refresh Control Unit Operation Set E Bit Figure 7-3.Refresh Address Formation 7.4REFRESH ADDRESSESREFRESH CONTROL UNIT 7.5REFRESH BUS CYCLES 7.6GUIDELINES FOR DESIGNING DRAM CONTROLLERSREFRESH CONTROL UNIT Table 7-1.Identification of Refresh Bus CyclesT3/TW 7.7PROGRAMMING THE REFRESH CONTROL UNIT 7.7.1Calculating the Refresh Interval7.7.2Refresh Control Unit Registers REFRESH CONTROL UNITRegister Mnemonic RFBASERegister Name:Refresh Base Address Register Refresh Clock Interval Register RFTIMESets refresh rate Register Name7.7.3Programming Example Register Name Register Mnemonic Register FunctionRefresh Control Register RFCON Controls Refresh Unit operationREFRESH CONTROL UNIT Example 7-1.Initializing the Refresh Control Unit7.8REFRESH OPERATION AND BUS HOLD REFRESH CONTROL UNITCLKOUT Page Interrupt Control Unit Page CHAPTER INTERRUPT CONTROL UNIT 8.1FUNCTIONAL OVERVIEW8.2MASTER MODE 8.2.1Generic Functions in Master ModeTable 8-1.Default Interrupt Priorities INTERRUPT CONTROL UNIT 8.2.1.1Interrupt Masking8.2.1.2Interrupt Priority Interrupt NameINTERRUPT CONTROL UNIT 8.2.1.3Interrupt Nesting8.3.1Typical Interrupt Sequence 8.3FUNCTIONAL OPERATION IN MASTER MODE8.3.2Priority Resolution •the Interrupt Control Unit has been initialized 8.3.2.2Interrupts That Share a Single Source 8.3.3Cascading with External 8259AsINTERRUPT CONTROL UNIT INT0 8.3.4Interrupt Acknowledge Sequence 8.3.5PollingINTERRUPT CONTROL UNIT Table 8-2.Fixed Interrupt Types8.3.6Edge and Level Triggering 8.3.7Additional Latency and Response Time8.4PROGRAMMING THE INTERRUPT CONTROL UNIT 8.4.1Interrupt Control Registers INTERRUPT CONTROL UNITRegister Mnemonic: TCUCON, DMA0CON, DMA1CON I2CON, I3CON Register MnemonicINTERRUPT CONTROL UNIT I0CON, I1CONRegister Mnemonic 8.4.2Interrupt Request Register Interrupt Request RegisterREQST Stores pending interrupt requestsInterrupt Mask Register IMASKMasks individual interrupt sources 8.4.4Priority Mask Register8.4.5In-ServiceRegister Register NamePriority Mask Register Register Mnemonic8.4.6Poll and Poll Status Registers Figure 8-10. In-ServiceRegisterRegister Name Register MnemonicRegister Name Register Mnemonic Register Function Poll Register POLLINTERRUPT CONTROL UNIT Figure 8-11.Poll Register8.4.7End-of-InterruptEOI Register Read to check for pending interrupts when pollingRegister Name Register Mnemonic Register Function Poll Status Register POLLSTS8.4.8Interrupt Status Register Used to issue an EOI commandRegister Name Register Mnemonic Register Function End-of-InterruptRegister EOIInterrupt Status Register INTSTS 8.5SLAVE MODERegister Name Register Mnemonic Register Function Figure 8-15.Interrupt Control Unit in Slave Mode INT0 INTA 80186 Modular Core Select IRQ8259A 82C59A8.5.1Slave Mode Programming 8.5.1.1Interrupt Vector Register Table 8-5.Slave Mode Fixed Interrupt Type BitsINTERRUPT CONTROL UNIT INTVEC Register MnemonicINTERRUPT CONTROL UNIT 8.5.1.2End-Of-InterruptRegisterEnd-of-InterruptRegister in Slave Mode Used to issue the EOI commandRegister Name Register Mnemonic8.5.2Interrupt Vectoring in Slave Mode Interrupt presented to Interrupt Control Unit INTERRUPT CONTROL UNIT Page Timer/Counter Unit Page CHAPTER TIMER/COUNTER UNIT 9.1FUNCTIONAL OVERVIEWT0 In T1IN T0OUT T1OUT TIMER/COUNTER UNITT0IN TIMER/COUNTER UNIT Figure 9-3.Timers 0 and 1 Flow ChartTIMER/COUNTER UNIT Figure 9-3.Timers 0 and 1 Flow Chart Continued9.2PROGRAMMING THE TIMER/COUNTER UNIT Dual Maximum Count ModeSingle Maximum Count Mode Maxcount ATimer 0 and 1 Control Registers T0CON, T1CON Defines Timer 0 and 1 operationTIMER/COUNTER UNIT Figure 9-5.Timer 0 and Timer 1 Control RegistersTIMER/COUNTER UNIT Register Name Register Mnemonic Register FunctionTimer 2 Control Register T2CON Defines Timer 2 operationTIMER/COUNTER UNIT Figure 9-6.Timer 2 Control RegisterTimer Count Register Contains the current timer countT0CNT, T1CNT, T2CNT TIMER/COUNTER UNIT9.2.1Initialization Sequence 9.2.2Clock Sources 9.2.3Counting ModesTIMER/COUNTER UNIT Table 9-1.Timer 0 and 1 Clock SourcesTIMER/COUNTER UNIT 9.2.3.1RetriggeringTable 9-2.Timer Retriggering 9.2.4Pulsed and Variable Duty Cycle OutputTIMER/COUNTER UNIT 9.2.5Enabling/Disabling Counters Timer Serviced 1Internal Count Value Maxcount -9.2.6Timer Interrupts 9.3.1Input Setup and Hold Timings9.2.7Programming Considerations 9.3TIMING9.3.2Synchronization and Maximum Frequency 9.3.3Real-TimeClock9.3.4Square-WaveGenerator 9.3.5Digital One-ShotTIMER/COUNTER UNIT Example 9-1.Configuring a Real-TimeClockTIMER/COUNTER UNIT TIMER/COUNTER UNIT enable interruptsTIMER/COUNTER UNIT Example 9-2.Configuring a Square-WaveGeneratorTIMER/COUNTER UNIT Example 9-3.Configuring a Digital One-ShotTIMER/COUNTER UNIT Page Direct Memory Access Unit Page 10.1.1 The DMA Transfer CHAPTER DIRECT MEMORY ACCESS UNIT10.1 FUNCTIONAL OVERVIEW Fetch 10.1.2 Source and Destination Pointers 10.1.3 DMA Requests10.1.4 External Requests Fetch Cycle 10.1.5.1Timer 2-InitiatedTransfers 10.1.5 Internal Requests10.1.6 DMA Transfer Counts DIRECT MEMORY ACCESS UNIT10.1.7.1Termination at Terminal Count 10.1.7.2Software Termination10.1.10 The Two-ChannelDMA Unit 10.1.8 DMA Unit Interrupts10.1.9 DMA Cycles and the BIU Module 10.2 PROGRAMMING THE DMA UNIT 10.2.1 DMA Channel ParametersRegister Mnemonic DxSRCHRegister Name:DMA Source Address Pointer High Register Mnemonic DxSRCLRegister Name:DMA Source Address Pointer Low DIRECT MEMORY ACCESS UNIT Register MnemonicDxDSTH Register FunctionRegister Mnemonic DxDSTLRegister Name:DMA Destination Address Pointer Low DMA Control Register DxCONControls DMA channel parameters DIRECT MEMORY ACCESS UNITDIRECT MEMORY ACCESS UNIT Register NameDMA Control Register Register MnemonicRegister Name DMA Control RegisterRegister Mnemonic DxCONDIRECT MEMORY ACCESS UNIT 10.2.1.4Arming the DMA Channel10.2.1.5Selecting Channel Synchronization 10.2.1.6Programming the Transfer Count OptionsDMA Transfer Count DxTCContains the DMA channel’s transfer count Register Name10.2.2 Suspension of DMA Transfers 10.2.3 Initializing the DMA Unit10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT 10.3.1 DRQ Pin Timing Requirements10.3.2 DMA Latency 10.3.3 DMA Transfer Rates10.3.4 Generating a DMA Acknowledge 10.4 DMA UNIT EXAMPLESDIRECT MEMORY ACCESS UNIT Example 10-1.Initializing the DMA UnitDIRECT MEMORY ACCESS UNIT Example 10-1.Initializing the DMA Unit ContinuedSECTORS DIRECT MEMORY ACCESS UNITExample 10-1.Initializing the DMA Unit Continued DIRECT MEMORY ACCESS UNIT Example 10-2.Timed DMA TransfersDIRECT MEMORY ACCESS UNIT Example 10-2.Timed DMA Transfers ContinuedPage Math Coprocessing Page 11.2 AVAILABILITY OF MATH COPROCESSING CHAPTER MATH COPROCESSING11.1 OVERVIEW OF MATH COPROCESSING 11.3 THE 80C187 MATH COPROCESSOR 11.3.1 80C187 Instruction Set•the 80C187 uses register or memory operands MATH COPROCESSING Table 11-2.80C187 Arithmetic InstructionsAddition DivisionMATH COPROCESSING 11.3.1.3Comparison Instructions Table 11-3.80C187 Comparison Instructions11.3.1.4Transcendental Instructions Table 11-4.80C187 Transcendental InstructionsMATH COPROCESSING 11.3.1.5Constant Instructions Table 11-5.80C187 Constant Instructions11.3.1.6Processor Control Instructions Table 11-6.80C187 Processor Control Instructions11.3.2 80C187 Data Types 11.4 MICROPROCESSOR AND COPROCESSOR OPERATIONMATH COPROCESSING Figure 11-1. 80C187-SupportedData TypesMATH COPROCESSING 80C187Modular Core11.4.2 Processor Bus Cycles Accessing the 80C187 11.4.1 Clocking the 80C187MATH COPROCESSING Table 11-7.80C187 I/O Port Assignments11.4.3 System Design Tips MATH COPROCESSING 80C187Modular Core11.4.4 Exception Trapping 11.5 EXAMPLE MATH COPROCESSOR ROUTINESMATH COPROCESSING 80C186Modular Core 80C187MATH COPROCESSING MATH COPROCESSING ONCE Mode Page CHAPTER ONCE MODE 12.1 ENTERING/LEAVING ONCE MODEONCE MODE Figure 12-1.Entering/Leaving ONCE Modebidirectional weakly held pins except OSCOUT NOTES: 1. Entering ONCE Mode 2.Latching ONCE Mode80C186 Instruction Set Additions and Extensions Page PUSHA/POPA A.1 80C186 INSTRUCTION SET ADDITIONSA.1.1 Data Transfer Instructions A.1.2 String Instructions INS source_string, portOUTS port, destination_string A.1.3 High-LevelInstructions1.Main has variables at fixed locations Figure A-3.Stack Frame for Main at Level Figure A-2.Variable Access in Nested Procedures80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS BPA = BP Value for Procedure A Figure A-4.Stack Frame for Procedure A at Level80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS BP SP80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS BP SPOld BP BPM BPM BPM BPA BPA BPM BPA BPB Display B Dynamic Storage BLEAVE 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSBOUND register, address A.2 80C186 INSTRUCTION SET ENHANCEMENTSA.2.1 Data Transfer Instructions PUSH dataA.2.2 Arithmetic Instructions IMUL destination, source, dataA.2.3 Bit Manipulation Instructions SAL destination, countROL destination, count ROR destination, countRCL destination, count RCR destination, countInput Synchronization Page B.1 WHY SYNCHRONIZERS ARE REQUIRED APPENDIX B INPUT SYNCHRONIZATIONB.2 ASYNCHRONOUS PINS Instruction Set Descriptions Page APPENDIX C INSTRUCTION SET DESCRIPTIONS Table C-1.Instruction Format VariablesINSTRUCTION SET DESCRIPTIONS Table C-2.Instruction OperandsOperand DescriptionINSTRUCTION SET DESCRIPTIONS Table C-3.Flag Bit FunctionsINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction SetADC dest, src INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedName DescriptionCall Procedure CALL procedure-nameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedClear Interrupt-enableFlag INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-10 NameC-11 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-12 NameWhen Source Operand is a Byte When Source Operand is a WordINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedProcedure Entry INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-14INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-15 NameWhen Source Operand is a Byte When Source Operand is a WordINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-17 IN accum, portINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-18 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-19 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-20 JA disp8INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedJAE disp8 JNB disp8INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedJE disp8 JZ disp8INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedJL disp8 JGE disp8INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedJNE disp8 JNZ disp8INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedJO disp8 JP disp8INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-26 LDS dest, srcLoad Pointer Using ES INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-27INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-28 LODS src-stringINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-29 MOV dest, srcINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-30 MOVS dest-string, src-stringC-31 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-32 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-33 NameC-34 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-35 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-36 NameC-37 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-38 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-39 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedSHL dest, count SAL dest, countINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-41 NameWhen Source Operand is a Byte When Source Operand is a WordINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-43 SHR dest, srcINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-44 STOS dest-stringINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-45 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-46 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-47 NamePage Instruction Set Opcodes and Clock Cycles Page Table D-1.Operand Variables APPENDIX D INSTRUCTION SET OPCODESAND CLOCK CYCLES INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set SummaryFunction FormatINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedDATA TRANSFER INSTRUCTIONS Continued ARITHMETIC INSTRUCTIONSARITHMETIC INSTRUCTIONS Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedARITHMETIC INSTRUCTIONS Continued BIT MANIPULATION INSTRUCTIONSINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedBIT MANIPULATION INSTRUCTIONS Continued Shifts/RotatesINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedPROGRAM TRANSFER INSTRUCTIONS Continued Iteration ControlINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedTable D-3.Machine Instruction Decoding Guide ByteINSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4.Mnemonic Encoding Matrix Left HalfD-21 INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-4.Mnemonic Encoding Matrix Right Half INSTRUCTION SET OPCODES AND CLOCK CYCLES AbbrDefinition AbbrIndex Page INDEX ARDY, See READY ArithmeticData bus, See Address and data bus INDEXCrystal‚ See Oscillator INDEX See also Bus cyclesSee also Refresh Control Unit Index-3interrupt INDEXIndex-4 INDEX Index-5INDEX Index-6Index-7 Timers‚ See Timer Counter Unit TCUINDEX INDEX Index-8