Intel 80C188XL, 80C186XL user manual UCS Control Register, Umcs, Controls the operation Chip-select

CHIP-SELECT UNIT

Register Name:
	UCS Control Register
Register Mnemonic:	UMCS
Register Function:	Controls the operation of the		chip-select.
		UCS

15

U U 1 1 7 6

U U

11

54

U U

11

32

U U

11

10

		0
R	R	R
2	1	0

				A1141-0A
Bit	Bit Name	Reset	Function
Mnemonic		State
U17:10	Start	0FFH	Defines the starting address for the chip-select.
	Address		During memory bus cycles, U17:10 are
			compared with the A17:10 address bits. An
			equal to or greater than result enables the	UCS
			chip-select if A19:18 are both one. Table 6-2 on
			page 6-12 lists the only valid programming
			combinations.
R2	Bus Ready	0H	When R2 is clear, bus ready must be active to
	Disable		complete a bus cycle. When R2 is set, R1:0
			control the number of bus wait states and bus
			ready is ignored.
R1:0	Wait State	3H	R1:0 define the minimum number of wait states
	Value		inserted into the bus cycle.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Programming U17:10 with values other than those shown in Table 6-2 on page 6-12 results in unreliable chip-select operation. Reading this register (before writing it) enables the chip-select; however, none of the programmable fields will be properly initial- ized.

Figure 6-5. UMCS Register Definition

6-7