Intel 80C186XL, 80C188XL 2.1.3General Registers, OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

During periods when the Execution Unit is busy executing instructions, the Bus Interface Unit sequentially prefetches instructions from memory. As long as the prefetch queue is partially full, the Execution Unit fetches instructions.

2.1.3General Registers

The 80C186 Modular Core family CPU has eight 16-bit general registers (see Figure 2-3). The general registers are subdivided into two sets of four registers. These sets are the data registers (also called the H & L group for high and low) and the pointer and index registers (also called the P & I group).

		H			L
	15		8	7	0
			AX
		AH			AL
			BX
Data		BH			BL
Group			CX
		CH			CL
			DX
		DH			DL
			SP
Pointer			BP
and
Index
Group				SI

Accumulator

Base

Count

Data

Stack Pointer

Base Pointer

Source Index

DI

Destination Index

A1033-0A

Figure 2-3. General Registers

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