Intel 80C188XL, 80C186XL user manual Fetch Cycle

DIRECT MEMORY ACCESS UNIT

10.1.4.1Source Synchronization

Atypical source-synchronized transfer is shown in Figure 10-3. Most DMA-driven peripherals deassert their DRQ line only after the DMA transfer has begun. The DRQ signal must be deas- serted at least four clocks before the end of the DMA transfer (at the T1 state of the deposit phase) to prevent another DMA cycle from occurring. A source-synchronized transfer provides the source device at least three clock cycles from the time it is accessed (acknowledged) to deassert its request line if further transfers are not required.

	Fetch Cycle				Deposit Cycle
T1	T2	T3	T4	T1	T2	T3	T4
CLKOUT
DRQ (Case 1)				1
DRQ (Case 2)					2

NOTES:

1.Current source synchronized transfer will not be immediately followed by another DMA transfer.

2.Current source synchronized transfer will be immediately followed by another DMA transfer.

A1188-0A

Figure 10-3. Source-Synchronized Transfers

10.1.4.2Destination Synchronization

Adestination-synchronized transfer differs from a source-synchronized transfer by the addition of two idle states at the end of the deposit cycle (Figure 10-4). The two idle states extend the DMA cycle to allow the destination device to deassert its DRQ pin four clocks before the end of the cycle. If the two idle states were not inserted, the destination device would not be able to deassert its request in time to prevent another DMA cycle from occurring.

The insertion of two idle states at the end of a destination synchronization transfer has an impor- tant side effect. A destination-synchronized DMA channel gives up the bus during the idle

states, allowing any other bus master to gain ownership. This includes the CPU, the Refresh

Control Unit, an external bus master or another DMA channel.

10-5