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Intel 80C186XL, 80C188XL user manual Bpm Bpa Bpb

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80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS

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Intel 80C186XL, 80C188XL user manual Bpm Bpa Bpb

Contents

80C186XL/80C188XL Microprocessor User’s Manual 80C186XL/80C188XL Microprocessor User’s Manual Intel Corporation Contents Contents Power Management Setting the PCB Base LocationClock Generation LCSChapter Refresh Control Unit Programming the Interrupt Control Unit Functional Overview Programming the TIMER/COUNTER UnitFunctional Overview Chapter Math Coprocessing Chapter Once Mode Figures UCS Reset ConfigurationInterrupt Control Register for Noncascadable External Pins 10-9 Tables Flag Bit Functions Example ExamplesIntroduction Page Chapter Introduction Feature 80C186XL 80C186EA 80C186EB 80C186EC HOW to USE this ManualComparison of 80C186 Modular Core Family Products Related Documents and Software Related DocumentsDocument/Software Title Order No Electronic Support Systems FaxBack ServiceBulletin Board System BBS World Wide Web CompuServe ForumsTechnical Support Training Classes Product LiteraturePage Overview 80C186 Family Architecture Page Architectural Overview Chapter Overview of the 80C186 Family ArchitectureExecution Unit Simplified Functional Block Diagram of the 80C186 Family CPUPhysical Address Generation Bus Interface UnitGeneral Registers General RegistersImplicit Use of General Registers Segment RegistersOperations Segment Registers Instruction PointerFlags Memory Segmentation Register Mnemonic Register NamePSW Flags Register FunctionSegment Locations in Physical Memory Logical AddressesFffffh Data DS Code CS Stack SS Extra ES2BFH 2BEH 2BDH 2BCH 2BBH 2BAH Dynamically Relocatable Code Type of Memory Reference Default Alternate OffsetLogical Address Sources Segment Code Data Before After Relocation Code SegmentSegment Data Extra Reserved Memory and I/O Space Stack Implementation10. Stack Operation Instruction Set Software OverviewGeneral-Purpose Data Transfer InstructionsInput/Output Sahf 7 6 5 4 3 2 1 Lahf S Z U a U P U CPushf Popf U U O D I T S Z U a U P U C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1Subtraction AdditionMultiplication DivisionBit Manipulation Instructions Arithmetic Interpretation of 8-Bit NumbersHex Bit Pattern Unsigned Signed Unpacked Packed Binary ShiftsString Instructions Program Transfer Instructions String Instruction Register and Flag UseCX AL/AX Overview of the 80C186 Family Architecture Unconditional Transfers Conditional TransfersIteration Control InterruptsMnemonic Condition Tested Jump if… 10. Interpretation of Conditional TransfersProcessor Control Instructions Addressing Modes11. Processor Control Instructions Register and Immediate Operand Addressing ModesMemory Addressing Modes BIU 0000 Physical Addr13. Direct Addressing Opcode Mod R/M Displacement15. Based Addressing 14. Register Indirect AddressingRate Base Vac Displacement High Address Rate AgeBase Register Register Dept Div Employee Age17. Indexed Addressing 18. Accessing an Array with Indexed Addressing19. Based Index Addressing 20. Accessing a Stacked Array with Based Index Addressing Opcode Source EA Destination EA 12. Supported Data Types Data Types Used in the 80C186 Modular Core FamilyType Description BCD23 C186 Modular Core Family Supported Data Types Interrupt/Exception Processing Interrupts and Exception Handling3FC 3FEOverview of the 80C186 Family Architecture Stack Interrupt Enable BitPSW Trap FlagExceptions Maskable InterruptsInvalid Opcode Type Interrupt Latency Software InterruptsClocks Interrupt Response TimeTotal Interrupt and Exception PriorityNMI Execute Divide Service RoutineIret 29. Simultaneous NMI and Single Step Interrupts Trap Flag = ???30. Simultaneous NMI, Single Step and Maskable Interrupt Interrupt Enable Bit IE = Trap Flag TF =Page Bus Interface Unit Page Address and Data BUS Concepts Multiplexed Address and Data BUS1 16-Bit Data Bus MByte KBytes Physical Implementation Address Space forFffff Ffffe Ffffd Ffffc A190 D70 A191 D158A191 D158 BHE High Even Byte TransferOdd Byte Transfer D70 A0 Low A191 D158 BHE HighBit Data Bus Even Word Transfers A191 D158 BHE Low D70 A0 LowA191 D158 BHE Low First Bus CycleSecond Bus Cycle D70 A0 High A191 D158 BHE LowBit Data Bus Word Transfers Memory and I/O Interfaces2 8-Bit Bus Memory and I/O Requirements 1 16-Bit Bus Memory and I/O RequirementsBUS Cycle Operation Low Phase High Phase PhaseClkout ALE S20 Valid Status AD150 Address DataRequest Pending Bus ReadyHold Deasserted RES#Address/Status Phase Address Status Phase Or TW Or TI Data PhaseOr TI ClkoutS20 A1916ALE STB STBWait States Data PhaseClkout RD/ WR Or TW Or TIAD150 Valid Write Data Read Read Data S20 Ardy Clkout Srdy ReadyBUS Ready CS1 CS2 CS3 CS4 ALE Clkout Clock 16. Generating a Normally Ready Bus SignalIdle States Clkout Ardy Srdy18. Normally Ready System Timings Read Bus Cycles BUS CyclesRead Bus Cycle Types Read Cycle Critical Timing ParametersRfsh A158A150 DT/R DENAD70 O0-7 UCS27C256 LA151 AD158Write Bus Cycle Types A158 A150Status Bits Bus Cycle Type LA0 BHE LA151A014 O18 CS1 AD70 AD158 LCSWrite Cycle Critical Timing Parameters Interrupt Acknowledge Bus CycleLock DT/R DEN INTA0 INTA1BHE RD, WR INTA0 Inta INT0 IR0 IR7 PCS0 LA1 Processor 82C59ASystem Design Considerations Halt Bus Cycle 011 AD150 AD70 A158 A1916 Pins Pin StateRfsh = BHEClkout Hold Hlda Temporarily Exiting the Halt Bus StateAD150 AD70 A158 A1916 ControlBHE Rfsh S20 AD150 AD70 A158 A1916T3 TI TI TI TI T4 T1 T2 T3AD70 A158 RFSH=1System Design Alternatives NMI/INTxClkout RD,WR DT/R DEN Buffering the Data BusDT/ R DeviceCPU Local Bus Buffered Bus Buffer Buffered Data Bus AD70 MCS0Buffer Local Data Bus Synchronizing Software and Hardware EventsUsing a Locked Bus Queue Status Signal Decoding Using the Queue Status SignalsQueue Status No queue operation occurredEntering Bus Hold MULTI-MASTER BUS System DesignsFloat Signal Hold ConditionRD, W R Float BHE , S20 LockRefresh Operation During a Bus Hold BHE, S20 Clkout Hold Hlda DEN RD, WRDT/R Lock Latched Hlda Hlda Reset Hold PRE CLRExiting Hold DT/R, S20 A1916, Lock DEN RD, WR, BHEBUS Cycle Priorities BUS Interface Unit Page Peripheral Control Block Page PCB Relocation Register Peripheral Control RegistersRegister Name PCB Relocation Register Register Mnemonic Bit Bit Name Reset Function Mnemonic StateRelreg Peripheral Control Block Ready Signals and Wait States Accessing the Peripheral Control BlockReserved Locations Bus CyclesWord reads Bus OperationAccessing the Peripheral Control Registers Setting the PCB Base LocationAccessing Reserved Locations Writing the PCB Relocation RegisterConsiderations for the 80C187 Math Coprocessor Interface Page Clock Generation Power Management Page RES Clock GenerationCrystal Oscillator Oscillator Operation = Inverter Output Z 90˚ 180˚Crystal Connections to Microprocessor Values µH Third-Overtone Crystal Inductor L1Selecting Crystals Reset and Clock Synchronization Using an External OscillatorOutput from the Clock Generator 1µf typical Typical Ct = V 1 eCold Reset Waveform Clkout PCS60,NCSPower Management Clkout ResetRES Resync Entering Power-Save Mode Power-Save ModeEnables and sets clock division factor Power Save RegisterRegister Name Register Mnemonic Register Function PwrsavExample Power-Save Initialization Code 10. Power-Save Clock Transition Leaving Power-Save ModeSyntax Chip-Select Unit Page Common Methods for Generating CHIP-SELECTS CHIP-SELECT Unit Features and BenefitsCHIP-SELECT Unit Functional Overview Chip-Selects Using Addresses Directly Simple Decoder27C256 74AC138MCS2 MCS3MCS1 PCS1MCS30, LCS A1916 UCS, PC S60Srdy Ardy UCS 1AddressData Active For Top 1 KByte Memory Map 1MBInitialization Sequence ProgrammingChip-Select Unit Registers Control Register Alternate RegisterUmcs UCS Control RegisterControls the operation Chip-select Lmcs LCS Control RegisterMmcs MCS Control RegisterControls the operation Chip-selects MCSPacs PCS Control RegisterPCS Mpcs Register NameMCS and PCS Alternate Control RegisterX S UCS Active Range Programming the Active RangesUCS Block Size and Starting Address Umcs Field Block Size Starting Address U1710LCS Active Range LCS Active RangeMCS Active Range Lmcs Field Block Size Ending Address U1710Block Size Mmcs Start Address Kbytes Restrictions MCS Block Size and Start Address RestrictionsPCS Active Range Bus Wait State and Ready ControlWait State Ready R2 Control Bit Wait Wait State Value R10 State CounterOverlapping Chip-Selects Programming Considerations Memory or I/O Bus Cycle DecodingCHIP-SELECTS and BUS Hold Example 1 Typical System ConfigurationExamples 13. Typical System MOD186XREF Name CSUEXAMPLE1 Example 6-1. Initializing the Chip-Select UnitDrambase EQU Place memory variables here Refresh Control Unit Page CLR REQ CPURefresh Control Unit Capabilities Role of the Refresh Control UnitRefresh Control Unit Operation Refresh Control Unit Operation Flow Chart Refresh Address Formation Refresh AddressesGuidelines for Designing Dram Controllers Refresh BUS CyclesIdentification of Refresh Bus Cycles Data Bus WidthMuxed Row Column Address S20 T3/TW ClkoutRAS CAS Calculating the Refresh Interval Programming the Refresh Control UnitRefresh Control Unit Registers Rfbase Register NameRefresh Base Address RegisterRegister FunctionDetermines upper 7 bits of refresh address Refresh Base Address RegisterRegister Function Sets refresh rate RftimeRfcon Refresh Control RegisterControls Refresh Unit operation Programming ExampleExample 7-1. Initializing the Refresh Control Unit Refresh Operation and BUS Hold RD, WR BHE, S2 DT / R A1916 Clkout Hold Hlda DENPage Interrupt Control Unit Page Functional Overview Chapter Interrupt Control UnitTimer 0 Timer 1 Timer Master ModeGeneric Functions in Master Mode DMAInterrupt Masking Default Interrupt PrioritiesInterrupt Priority Interrupt Name Relative PriorityInterrupt Nesting Priority Resolution Functional Operation in Master ModeTypical Interrupt Sequence Priority Resolution Example Interrupts That Share a Single Source Cascading with External 8259AsInta INTA0 INT INT0INT INT1 Inta INTA1Polling Interrupt Acknowledge SequenceFixed Interrupt Types Interrupt Name Interrupt TypeAdditional Latency and Response Time Edge and Level TriggeringInta Idle Read IP Inta IdleRead CS Idle Push Flags Push CS Push IP Programming the Interrupt Control Unit2CH Interrupt Control Registers2AH MSK Interrupt Control Register for Internal SourcesI2CON, I3CON Register NameInterrupt Control Register non-cascadable pinsLVL I0CON, I1CON Register NameInterrupt Control Register cascadable pinsSfnm CASRegister Name Interrupt Request Register Register Mnemonic Interrupt Request RegisterReqst Register Function Stores pending interrupt requestsImask Register Name Interrupt Mask Register Register MnemonicRegister Function Masks individual interrupt sources Priority Mask RegisterPriority Mask Register In-Service RegisterPrimsk Masks lower-priority interrupt sourcesInserv In-Service RegisterIndicates which interrupt handlers are in process Poll and Poll Status RegistersPoll Poll RegisterIreq Poll Status Register Read to check for pending interrupts when pollingPollsts End-of-Interrupt EOI RegisterEnd-of-Interrupt Register Used to issue an EOI commandEOI Interrupt Status RegisterInterrupt Status Register Slave ModeIntsts DhltIRQ INT VCC INT0 Inta16. Interrupt Sources in Slave Mode Slave Mode ProgrammingMaster Mode Slave Mode PCB Offset Register Name Slave Mode Fixed Interrupt Type BitsInterrupt Vector Register Interrupt Control Unit Register ComparisonIntvec Register NameInterrupt Vector Register Slave Mode onlyUsed to issue the EOI command End-of-Interrupt Register in Slave ModeT1 T2 T3 T4 Interrupt Vectoring in Slave ModeInta INTA0 Select Lock CAS20 Slave Cascade Address From 8259AInta Idle Read IP Read CS Push Flags Push CS Push IP Initializing the Interrupt Control Unit for Master ModePriorities are used Page Timer/Counter Unit Page Chapter TIMER/COUNTER Unit Interrupt Latch Clock Timer Element Registers Output LatchT0IN T1IN T0OUT T1OUT Counter Element Multiplexing and Timer Input SynchronizationTimers 0 and 1 Flow Chart From Timer/Counter Unit Output Modes Programming the TIMER/COUNTER UnitDefines Timer 0 and 1 operation Timer 0 and 1 Control RegistersT0CON, T1CON EXT RTGALT ContDefines Timer 2 operation Timer 2 Control RegisterT2CON Maximum count. The MC bit must be clearedRegister Function Contains the current timer count Register Name Timer Count Register Register MnemonicT0CNT, T1CNT, T2CNT C CTimer Maxcount Compare Registers Clock Sources Timer 0 and 1 Clock SourcesCounting Modes Clock SourceRetriggering Timer Operation Timer RetriggeringPulsed and Variable Duty Cycle Output Enabling/Disabling Counters Timer Serviced Internal Count Value Maxcount TxOUT PinInput Setup and Hold Timings Timer InterruptsTiming Synchronization and Maximum Frequency Timer/Counter Unit Application ExamplesReal-Time Clock Square-Wave GeneratorIntsts Example 9-1. Configuring a Real-Time ClockOut Dx, al Timer2interruptroutine proc far T1CON Example 9-2. Configuring a Square-Wave GeneratorExample 9-3. Configuring a Digital One-Shot Cmpb Page Direct Memory Access Unit Page DMA Transfer Chapter Direct Memory Access UnitTypical DMA Transfer Fetch DepositDMA Requests Source and Destination PointersDMA Transfer Directions Byte and Word TransfersT1 or T2 or T3 or TW or T4 or External RequestsCycle DRQSource Synchronization DRQ CaseFetch Cycle Deposit Cycle T1 T2 T3 T4 T1 T2 T3 T4 TI TI Timer 2-Initiated TransfersClkout DRQ CaseTermination and Suspension of DMA Transfers DMA Transfer CountsDMA Cycles and the BIU DMA Unit InterruptsTwo-Channel DMA Unit DMA Channel ArbitrationTwo-Channel DMA Module ModuleProgramming the DMA Unit SRCDMA Channel Parameters Register Mnemonic DxSRCH Register NameDMA Source Address Pointer HighDMA Xxxxh Register Mnemonic DxSRCL Register NameDMA Source Address Pointer LowS S a a DxDSTH Register NameDMA Destination Address Pointer HighContains the upper 4 bits of the DMA Destination pointer Register Mnemonic DxDSTL Register NameDMA Destination Address Pointer LowDmem D I E N C C C N TDdec DincIdrq Synchronization TypeStrt CHGWord Selecting Channel Synchronization Arming the DMA ChannelProgramming the Transfer Count Options Generating Interrupts on Terminal Count Setting the Relative Priority of a ChannelInitializing the DMA Unit Suspension of DMA TransfersHardware Considerations and the DMA Unit DRQ Pin Timing RequirementsDMA Transfer Rates DMA LatencyDMA Unit Examples Generating a DMA AcknowledgeMOV DS, AX Assume Dsdataseg Example 10-1. Initializing the DMA Unit10-24 10-25 Example 10-2. Timed DMA Transfers 10-27 Page Math Coprocessing Page Availability of Math Coprocessing Overview of Math Coprocessing11.3.1 80C187 Instruction Set 80C187 Math CoprocessorReal Transfers C187 Data Transfer InstructionsInteger Transfers Packed Decimal TransfersOther Operations C187 Arithmetic InstructionsC187 Comparison Instructions Comparison InstructionsTranscendental Instructions C187 Transcendental InstructionsC187 Constant Instructions Constant InstructionsC187 Processor Control Instructions Fldz FLD1 Fldpi FLDL2T FLDL2E FLDLG2 FLDLN2Microprocessor and Coprocessor Operation 11.3.2 80C187 Data TypesC187-Supported Data Types Modular Core 80C18780C186 Clocking the 80C187 Processor Bus Cycles Accessing the 80C187C187 I/O Port Assignments Address Read Definition Write DefinitionSystem Design Tips C187 Configuration with a Partially Buffered Bus Example Math Coprocessor Routines Exception TrappingC187 Exception Trapping via Processor Interrupt Pin 80C186 Modular CoreName Example80C187init Results Example 11-2. Floating Point Math Routine Using FsincosOnce Mode Page ENTERING/LEAVING Once Mode Chapter Once ModeOscout RES UCS LCS80C186 Instruction Set Additions Extensions Page Data Transfer Instructions 80C186 Instruction SET AdditionsHigh-Level Instructions String InstructionsFigure A-1. Formal Definition of Enter Figure A-2. Variable Access in Nested Procedures Figure A-4. Stack Frame for Procedure a at Level BPM BPA BPB Leave 80C186 Instruction SET Enhancements Bound register, addressBit Manipulation Instructions Arithmetic InstructionsShift Instructions Rotate Instructions ROL destination, countInput Synchronization Page Figure B-1. Input Synchronization Circuit WHY Synchronizers are RequiredAsynchronous Pins Instruction Set Descriptions Page Variable Description Table C-1. Instruction Format VariablesOperand Description Table C-2. Instruction OperandsTable C-3. Flag Bit Functions Table C-4. Instruction Set AAS Ascii Adjust for SubtractionADC Add with CarryADD dest, src ADDLogical Dest, srcCall procedure-name Call ProcedureBound Detect Value Out of RangeClear Carry flag Convert Byte to WordClear Direction flag Complement Carry Flag Clear Interrupt-enable FlagCompare CMPCMP dest, src Compare StringDecimal Adjust for Subtraction Decimal Adjust for AdditionConvert Word to Doubleword Decrement DECWhen Source Operand is a Word Divide When Source Operand is a ByteEnter locals, levels Procedure EntryEscape Halt Integer Divide When Source Operand is a Byte Input Byte or Word When Source Operand is a Byte Integer Multiply When Source Operand is a ByteImul Accum, portIncrement INCString INS dest-string, portINT interrupt-type InterruptInterrupt Return Interrupt on OverflowJump on Above Jump on Not Below or EqualJump on Not Below Jump on Above or EqualJump on Below Jump on Not Above or EqualJump on Equal Jump on Zero Jump if CX ZeroJump on Greater Than Jump on Not Less Than or EqualJump on Not Greater Than or Equal Name Description Operation Flags Affected Jump on Less ThanJump on Less Than or Equal Jump on Not Greater ThanJump on Not Zero Jump on Not EqualJump on Not Overflow Jump on Not SignJump on Parity Name Description Operation Flags Affected Jump on OverflowJump on Parity Equal Instruction FormatLDS dest, src Load Pointer Using DSLoad Effective Address LEA dest, srcLES dest, src Load Pointer Using ESLock the Bus Lods src-string Load String Byte or Word When Source Operand is a ByteLoop Loop While EqualLoop While Not Zero Loop While Not EqualMove Byte or Word MOV dest, srcMove String Multiply When Source Operand is a ByteMovs dest-string, src-string MULLogical Not When Source Operand is a Byte Negate When Source Operand is a ByteNEG Or dest,src Name Description Operation Flags Affected Logical orOutput OUT port, accumulatorOuts port, srcstring Out StringPop Pop Flags Pop AllPush Push Flags Push AllRCL dest, count Rotate Through Carry LeftRotate Through Carry Right RCR dest, countRepeat While Equal RepeatRepeat While Zero Repeat While Not EqualReturn RETRET optional-pop-value Rotate LeftROR dest, count Rotate RightStore Register AH Into Flags Shift Arithmetic Left Shift Logical LeftShift Arithmetic Right Subtract With Borrow SBBSBB dest, src Scas dest-string Scan String When Source Operand is a ByteSHR dest, src Shift Logical RightSet Carry Flag Set Direction FlagStore Byte or Word String When Source Operand is a Byte Set Interrupt-enable FlagStos dest-string Subtract SUBSUB dest, src TestExchange WaitXchg dest, src Xlat translate-table TranslateExclusive Or XOR dest, srcPage Instruction Set Opcodes and Clock Cycles Page EA Calculation Table D-1. Operand VariablesMod Effect on EA Calculation Reg Bit w=1 Bit w=0Function Format Clocks Table D-2. Instruction Set SummaryArithmetic Instructions Arithmetic Instructions BIT Manipulation Instructions String Manipulation Instructions JB/JNAE = LOOPNZ/LOOPNE = Processor Control Instructions Table D-3. Machine Instruction Decoding GuideInstruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles AX,CX Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles AL,DX Instruction SET Opcodes and Clock Cycles Table D-4. Mnemonic Encoding Matrix Left Half Table D-4. Mnemonic Encoding Matrix Right Half Abbr Definition Table D-5. Abbreviations for Mnemonic Encoding MatrixIndex Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8