Intel 80C188XL, 80C186XL Chapter Chip-Selectunit, 6.1COMMON METHODS FOR GENERATING CHIP-SELECTS

CHAPTER 6

CHIP-SELECT UNIT

Every system requires some form of component-selection mechanism to enable the CPU to ac- cess a specific memory or peripheral device. The signal that selects the memory or peripheral de- vice is referred to as a chip-select. Besides selecting a specific device, each chip-select can be used to control the number of wait states inserted into the bus cycle. Devices that are too slow to keep up with the maximum bus bandwidth can use wait states to slow the bus down.

6.1COMMON METHODS FOR GENERATING CHIP-SELECTS

One method of generating chip-selects uses latched address signals directly. An example inter- face is shown in Figure 6-1(A). In the example, an inverted A16 is connected to an SRAM device with an active-low chip-select. Any bus cycle with an address between 10000H and 1FFFFH (A16 = 1) enables the SRAM device. Also note that any bus cycle with an address starting at 30000H, 50000H, 70000H and so on also selects the SRAM device.

Decoding more address bits solves the problem of a chip-select being active over multiple address ranges. In Figure 6-1(B), a one-of-eight decoder is connected to the uppermost address bits. Each decoded output is active for one-eighth of the 1 Mbyte address space. However, each chip-select has a fixed starting address and range. Future system memory changes could require circuit changes to accommodate the additional memory.

6.2CHIP-SELECT UNIT FEATURES AND BENEFITS

The Chip-Select Unit overcomes limitations of the designs shown in Figure 6-1 and has the fol- lowing features:

•Ten chip-select outputs

•Programmable start and stop addresses

•Memory or I/O bus cycle decoder

•Programmable wait-state generator

•Provision to disable a chip-select

•Provision to override bus ready

Figure 6-2 illustrates the logic blocks that generate a chip-select. Each chip-select has a duplicate set of logic.

6-1