Manuals / Intel / Computer Equipment / Computer Hardware

Intel 80C186XL, 80C188XL user manual T0 In

Models: 80C186XL 80C188XL

1 405

Page 231

TIMER/COUNTER UNIT

	T0 In			T1 In
	Transition Latch/		Transition Latch/
	Synchronizer			Synchronizer
	Timer 0				T0
	Registers			Output Latch	T0
	Registers	Counter		Output Latch	Out
CPU	Timer 1	Counter			Out
CPU	Timer 1	Element
	Registers	Element
	Registers				T1
	Timer 2			Output Latch	T1
	Timer 2			Output Latch	Out
	Registers				Out
	Registers
	CPU			Interrupt
	CPU			Latch
	Clock			Latch
	Clock
					A1292-0A

Figure 9-1. Timer/Counter Unit Block Diagram

9-2

Page 231

Image 231

Intel 80C186XL, 80C188XL user manual T0 In

Contents

80C186XL/80C188XL Microprocessor User’s Manual 1995 80C186XL/80C188XL Microprocessor User’s ManualIntel Corporation Literature Sales P.O. Box CHAPTER CONTENTSCHAPTER INTRODUCTIONCONTENTS CHAPTERBUS INTERFACE UNIT PERIPHERAL CONTROL BLOCK CONTENTSCLOCK GENERATION AND POWER MANAGEMENT CHAPTERCHAPTER CONTENTSCHAPTER REFRESH CONTROL UNITCHAPTER CONTENTSTIMER/COUNTER UNIT DIRECT MEMORY ACCESS UNITCONTENTS CHAPTERMATH COPROCESSING APPENDIX A CONTENTSONCE MODE CHAPTERPage FIGURESCONTENTS FigurePage CONTENTSFIGURES FigurePage CONTENTSFIGURES FigurePage CONTENTSFIGURES FigurePage TABLESCONTENTS TablePage CONTENTSTABLES TablePage EXAMPLESCONTENTS ExampleIntroduction Page CHAPTER INTRODUCTION INTRODUCTION 1.1HOW TO USE THIS MANUAL1.2RELATED DOCUMENTS INTRODUCTIONTable 1-2.Related Documents and Software 1.3ELECTRONIC SUPPORT SYSTEMS 1.3.1FaxBack Service1.3.2Bulletin Board System BBS 1.3.3CompuServe Forums 1.3.4World Wide Web1.4TECHNICAL SUPPORT 1.6TRAINING CLASSES 1.5PRODUCT LITERATUREPage Overview of the 80C186 Family Architecture Page CHAPTER OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.1ARCHITECTURAL OVERVIEW OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.1Execution Unit2.1.2Bus Interface Unit 2.1.3General Registers OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-3.General Registers 2.1.4Segment Registers OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-1.Implicit Use of General Registers 2.1.5Instruction Pointer OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-4.Segment Registers 2.1.6Flags 2.1.7Memory Segmentation Reset Register NameRegister Mnemonic Register Function2.1.8Logical Addresses C F H I Data: DS Code: CS Stack: SS Extra: ESB E H J FFFFFH A B D E G J K 0H2C4H 2C3H 2C2H 2C1H 2C0H 2BFH 2BEH 2BDH 2BCH 2BBH Physical Address Offset 3H Segment Base LogicalAddresses Segment Base Offset 13H2.1.9Dynamically Relocatable Code OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-2.Logical Address Sources Before 2.1.11 Reserved Memory and I/O Space 2.1.10 Stack ImplementationFigure 2-10.Stack Operation OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1Instruction Set 2.2SOFTWARE OVERVIEWGeneral-Purpose OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.1Data Transfer Instructions Table 2-3.Data Transfer Instructions2.2.1.2Arithmetic Instructions I = Interrupt Enable Flag T = Trap FlagOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Figure 2-11.Flag Storage FormatSubtraction OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-4.Arithmetic Instructions AdditionBit Pattern OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.3Bit Manipulation Instructions Table 2-6.Bit Manipulation InstructionsOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.4String InstructionsTable 2-7.String Instructions Scan value Destination for LODS Source for STOS OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.5Program Transfer Instructions SI DI CX AL/AX DF ZFUnconditional transfer instructions can transfer control either to a target instruction within the current code segment intrasegment transfer or to a different code segment intersegment trans- fer. The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans- fer FAR. The transfer is made unconditionally when the instruction is executed. CALL, RET and JMP are all unconditional transfers Unconditional Transfers OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-9.Program Transfer Instructions Conditional Transfers“Jump if…” OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREMnemonic Condition TestedTable 2-11.Processor Control Instructions 2.2.2Addressing ModesOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.6Processor Control Instructions2.2.2.2Memory Addressing Modes OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREEncoded in the Instruction Explicit in the OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE DisplacementOpcode Mod R/MBX or BP DisplacementOpcode Mod R/MDisplacement Opcode BX or BP DisplacementOpcode Mod R/MHigh Address Port Address Direct Port Addressing Opcode SI DISource EA Destination EA Opcode DataDescription OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-12.Supported Data Types TypeOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE External Interrupt Sources NMI CPUMaskable Interrupt Request Interrupt Acknowledge Interrupt Control UnitFigure 2-25.Interrupt Vector Table OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE3.The current CS and IP are pushed onto the stack Stack PSW 2.3.1.2Maskable Interrupts Divide Error — TypeSingle Step — Type OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREArray Bounds Check — Type Numerics Coprocessor Fault — TypeBreakpoint Interrupt — Type Interrupt on Overflow — Type2.3.3Interrupt Latency 2.3.2Software Interrupts2.3.5Interrupt and Exception Priority 2.3.4Interrupt Response TimeClocks TotalService Routine IRET Divide ErrorPush PSW, CS, IP Fetch Divide Error Vector Service Routine IRET Execute DivideTrap Flag = Push PSW, CS, IP Fetch Divide Error VectorService Routine IRET Trap Flag = ??? NMI InstructionInterrupt Enable Bit IE = Trap Flag TF = Page Bus Interface Unit Page 3.2.116-BitData Bus CHAPTER BUS INTERFACE UNIT3.1MULTIPLEXED ADDRESS AND DATA BUS 3.2ADDRESS AND DATA BUS CONCEPTS1 MByte 512 KBytes512 KBytes Odd Byte Transfer Even Byte TransferBUS INTERFACE UNIT A19:1D15:8 BHE D7:0 A0 LowFirst Bus Cycle Second Bus Cycle3.2.28-BitData Bus First Bus Cycle A19:0D7:0 3.3MEMORY AND I/O INTERFACES3.3.116-BitBus Memory and I/O Requirements 3.3.28-BitBus Memory and I/O Requirements3.4BUS CYCLE OPERATION Rising PhaseCLKOUT FallingBus Ready 3.4.1Address/Status Phase or TI Signals From CPU 3.4.3Wait States 3.4.2Data Phaseor TW T1 T2 T3 TW TW T4 CLKOUT READY CS1 CS2 CS3 CS4 ALE CLKOUTWait State Module Input Input Clear ClockCLKOUT Wait State Module CS1 Enable CS2Load READY3.4.4Idle States CLKOUTARDY SRDY •The instruction prefetch queue is full Table 3-2. Read Bus Cycle Types 3.5BUS CYCLES3.5.1Read Bus Cycles BUS INTERFACE UNITCLKOUT 27C256 3.5.2Write Bus Cycles27C256 CLKOUT BUS INTERFACE UNIT LA15:1 RD LA0 WR BHEA0:14 OE I/O1:8 WE CS1 A0:14 OE I/O1:8 WE AD7:0 AD15:83.5.3Interrupt Acknowledge Bus Cycle BUS INTERFACE UNITTable 3-5.Write Cycle Critical Timing Parameters T3 T4 CLKOUT ALE S2:0 INTA0 INTA1 AD15:0 AD7:0 LOCKDT/R DEN A19:16 A15:8 BHE RD, WR T1 T2Processor 3.5.4HALT Bus Cycle CLKOUT 3.5.5Temporarily Exiting the HALT Bus State CLKOUT HOLD HLDA AD15:0 AD7:0 A15:8 A19:16CONTROL CLKOUT ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHE RFSHBUS INTERFACE UNIT 3.5.6Exiting HALT RFSH 3.6SYSTEM DESIGN ALTERNATIVESCLKOUT NMI/INTx ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHE3.6.1Buffering the Data Bus A19:16 3.6.2Synchronizing Software and Hardware Events 3.6.3Using a Locked Bus 3.6.4Using the Queue Status Signals Table 3-7.Queue Status Signal DecodingBUS INTERFACE UNIT Figure 3-33.Queue Status Timing 3.7MULTI-MASTERBUS SYSTEM DESIGNS3.7.1Entering Bus HOLD BUS INTERFACE UNITCLKOUT 3.7.1.2Refresh Operation During a Bus HOLD BUS INTERFACE UNITCLKOUT Latched HLDA 3.7.2Exiting HOLD+5 HLDA RESET HOLD PRE DQ CLR3.8BUS CYCLE PRIORITIES 9.DMA bus cycles Page Peripheral Control Block Page CHAPTER PERIPHERAL CONTROL BLOCK 4.1PERIPHERAL CONTROL REGISTERS4.2PCB RELOCATION REGISTER Register Name PCB Relocation RegisterRELREG Relocates the PCB within memory or I/O spaceFunction PERIPHERAL CONTROL BLOCKTable 4-1.Peripheral Control Block Function4.4.1Bus Cycles 4.4ACCESSING THE PERIPHERAL CONTROL BLOCK4.4.2READY Signals and Wait States 4.3RESERVED LOCATIONSByte reads 4.4.3F-BusOperationWord reads addressPERIPHERAL CONTROL BLOCK 4.5SETTING THE PCB BASE LOCATION4.4.3.2Accessing the Peripheral Control Registers 4.4.3.3Accessing Reserved LocationsPage Page Clock Generation and Power Management Page CHAPTER CLOCK GENERATION AND POWER MANAGEMENT 5.1CLOCK GENERATION5.1.1Crystal Oscillator 5.1.1.1Oscillator Operation CLOCK GENERATION AND POWER MANAGEMENTZ0 = Inverter Output Z 180˚Fundamental Third-OvertoneCrystal CLOCK GENERATION AND POWER MANAGEMENTFigure 5-4.Equations for Crystal Calculations CLKOUT5.1.1.2Selecting Crystals CLOCK GENERATION AND POWER MANAGEMENT5.1.2Using an External Oscillator 5.1.4Reset and Clock Synchronization5.1.3Output from the Clock Generator 50 k typical RESET IN 1µf typicalCLOCK GENERATION AND POWER MANAGEMENT Figure 5-5.Simple RC Circuit for Powerup ResetX1 Vcc CLOCK GENERATION AND POWER MANAGEMENTRESET Figure 5-6.Cold Reset WaveformFigure 5-7.Warm Reset Waveform CLOCK GENERATION AND POWER MANAGEMENT5.2POWER MANAGEMENT 5.2.1Power-SaveMode CLOCK GENERATION AND POWER MANAGEMENT5.2.1.1Entering Power-SaveMode CLOCK GENERATION AND POWER MANAGEMENT Register Name Register Mnemonic Register FunctionPower Save Register PWRSAV Enables and sets clock division factor 0 F F 15.2.1.2Leaving Power-SaveMode CLKOUT WRCLOCK GENERATION AND POWER MANAGEMENT Figure 5-10. Power-SaveClock TransitionCLOCK GENERATION AND POWER MANAGEMENT Chip-SelectUnit Page 6.2CHIP-SELECTUNIT FEATURES AND BENEFITS CHAPTER CHIP-SELECTUNIT6.1COMMON METHODS FOR GENERATING CHIP-SELECTS CHIP-SELECTUNIT 6.3CHIP-SELECTUNIT FUNCTIONAL OVERVIEWChip-SelectsUsing Chip-SelectsUsingInternal device EPROM or Flash memory types 1.The chip-selectis enabled 6.4.1Initialization Sequence 6.4PROGRAMMINGCHIP-SELECTUNIT Register NameRegister Mnemonic Register FunctionCHIP-SELECTUNIT Register NameRegister Mnemonic Register FunctionCHIP-SELECTUNIT Register NameRegister Mnemonic Register FunctionCHIP-SELECTUNIT Register NameRegister Mnemonic Register FunctionFigure 6-9.MPCS Register Definition MPCSRegister Mnemonic CHIP-SELECTUNIT6.4.2Programming the Active Ranges Table 6-4.MCS Active Range Table 6.3 LCS Active RangeCHIP-SELECTUNIT 6.4.2.2LCS Active Range 6.4.2.3MCS Active RangeStarting Address 6.4.3Bus Wait State and Ready Control CHIP-SELECTUNIT 6.4.2.4PCS Active RangeTable 6-6.PCS Active Range READY Wait State Ready 6.4.4Overlapping Chip-SelectsBUS READY R2 Control Bit Wait Wait State Value R1:0 State Counter6.4.6Programming Considerations 6.4.5Memory or I/O Bus Cycle Decoding6.5CHIP-SELECTSAND BUS HOLD 6.6.1Example 1: Typical System ConfigurationCSU Chip Select Device select External Master Chip SelectFigure 6-13.Typical System CHIP-SELECTUNITExample 6-1.Initializing the Chip-SelectUnit CHIP-SELECTUNITCHIP-SELECTUNIT Place memory variables here CHIP-SELECTUNITRefresh Control Unit Page CHAPTER REFRESH CONTROL UNIT 7.1THE ROLE OF THE REFRESH CONTROL UNIT 7.2REFRESH CONTROL UNIT CAPABILITIES7.3REFRESH CONTROL UNIT OPERATION Refresh Control Unit Operation Set E Bit 7.4REFRESH ADDRESSES REFRESH CONTROL UNITFigure 7-3.Refresh Address Formation Table 7-1.Identification of Refresh Bus Cycles 7.5REFRESH BUS CYCLES7.6GUIDELINES FOR DESIGNING DRAM CONTROLLERS REFRESH CONTROL UNITT3/TW REFRESH CONTROL UNIT 7.7PROGRAMMING THE REFRESH CONTROL UNIT7.7.1Calculating the Refresh Interval 7.7.2Refresh Control Unit RegistersRFBASE Register Name:Refresh Base Address RegisterRegister Mnemonic Register Name Refresh Clock Interval RegisterRFTIME Sets refresh rateControls Refresh Unit operation 7.7.3Programming ExampleRegister Name Register Mnemonic Register Function Refresh Control Register RFCONExample 7-1.Initializing the Refresh Control Unit REFRESH CONTROL UNITREFRESH CONTROL UNIT 7.8REFRESH OPERATION AND BUS HOLDCLKOUT Page Interrupt Control Unit Page 8.1FUNCTIONAL OVERVIEW CHAPTER INTERRUPT CONTROL UNIT8.2.1Generic Functions in Master Mode 8.2MASTER MODEInterrupt Name Table 8-1.Default Interrupt PrioritiesINTERRUPT CONTROL UNIT 8.2.1.1Interrupt Masking 8.2.1.2Interrupt Priority8.2.1.3Interrupt Nesting INTERRUPT CONTROL UNIT8.3FUNCTIONAL OPERATION IN MASTER MODE 8.3.2Priority Resolution8.3.1Typical Interrupt Sequence •the Interrupt Control Unit has been initialized 8.3.3Cascading with External 8259As INTERRUPT CONTROL UNIT8.3.2.2Interrupts That Share a Single Source INT0 Table 8-2.Fixed Interrupt Types 8.3.4Interrupt Acknowledge Sequence8.3.5Polling INTERRUPT CONTROL UNIT8.3.7Additional Latency and Response Time 8.3.6Edge and Level Triggering8.4PROGRAMMING THE INTERRUPT CONTROL UNIT INTERRUPT CONTROL UNIT 8.4.1Interrupt Control RegistersRegister Mnemonic: TCUCON, DMA0CON, DMA1CON Register Mnemonic I2CON, I3CONI0CON, I1CON Register MnemonicINTERRUPT CONTROL UNIT Stores pending interrupt requests 8.4.2Interrupt Request RegisterInterrupt Request Register REQST8.4.4Priority Mask Register Interrupt Mask RegisterIMASK Masks individual interrupt sourcesRegister Mnemonic 8.4.5In-ServiceRegisterRegister Name Priority Mask RegisterRegister Mnemonic 8.4.6Poll and Poll Status RegistersFigure 8-10. In-ServiceRegister Register NameFigure 8-11.Poll Register Register Name Register Mnemonic Register FunctionPoll Register POLL INTERRUPT CONTROL UNITPoll Status Register POLLSTS 8.4.7End-of-InterruptEOI RegisterRead to check for pending interrupts when polling Register Name Register Mnemonic Register FunctionEnd-of-InterruptRegister EOI 8.4.8Interrupt Status RegisterUsed to issue an EOI command Register Name Register Mnemonic Register Function8.5SLAVE MODE Register Name Register Mnemonic Register FunctionInterrupt Status Register INTSTS 82C59A Figure 8-15.Interrupt Control Unit in Slave ModeINT0 INTA 80186 Modular Core Select IRQ 8259A8.5.1Slave Mode Programming Table 8-5.Slave Mode Fixed Interrupt Type Bits INTERRUPT CONTROL UNIT8.5.1.1Interrupt Vector Register 8.5.1.2End-Of-InterruptRegister INTVECRegister Mnemonic INTERRUPT CONTROL UNITRegister Mnemonic End-of-InterruptRegister in Slave ModeUsed to issue the EOI command Register Name8.5.2Interrupt Vectoring in Slave Mode Interrupt presented to Interrupt Control Unit INTERRUPT CONTROL UNIT Page Timer/Counter Unit Page 9.1FUNCTIONAL OVERVIEW CHAPTER TIMER/COUNTER UNITT0 In TIMER/COUNTER UNIT T0INT1IN T0OUT T1OUT Figure 9-3.Timers 0 and 1 Flow Chart TIMER/COUNTER UNITFigure 9-3.Timers 0 and 1 Flow Chart Continued TIMER/COUNTER UNITMaxcount A 9.2PROGRAMMING THE TIMER/COUNTER UNITDual Maximum Count Mode Single Maximum Count ModeFigure 9-5.Timer 0 and Timer 1 Control Registers Timer 0 and 1 Control Registers T0CON, T1CONDefines Timer 0 and 1 operation TIMER/COUNTER UNITRegister Name Register Mnemonic Register Function TIMER/COUNTER UNITFigure 9-6.Timer 2 Control Register Timer 2 Control Register T2CONDefines Timer 2 operation TIMER/COUNTER UNITTIMER/COUNTER UNIT Timer Count RegisterContains the current timer count T0CNT, T1CNT, T2CNT9.2.1Initialization Sequence Table 9-1.Timer 0 and 1 Clock Sources 9.2.2Clock Sources9.2.3Counting Modes TIMER/COUNTER UNIT9.2.3.1Retriggering TIMER/COUNTER UNIT9.2.4Pulsed and Variable Duty Cycle Output TIMER/COUNTER UNITTable 9-2.Timer Retriggering Maxcount - 9.2.5Enabling/Disabling CountersTimer Serviced 1 Internal Count Value9.3TIMING 9.2.6Timer Interrupts9.3.1Input Setup and Hold Timings 9.2.7Programming Considerations9.3.5Digital One-Shot 9.3.2Synchronization and Maximum Frequency9.3.3Real-TimeClock 9.3.4Square-WaveGeneratorExample 9-1.Configuring a Real-TimeClock TIMER/COUNTER UNITTIMER/COUNTER UNIT enable interrupts TIMER/COUNTER UNITExample 9-2.Configuring a Square-WaveGenerator TIMER/COUNTER UNITExample 9-3.Configuring a Digital One-Shot TIMER/COUNTER UNITTIMER/COUNTER UNIT Page Direct Memory Access Unit Page CHAPTER DIRECT MEMORY ACCESS UNIT 10.1 FUNCTIONAL OVERVIEW10.1.1 The DMA Transfer Fetch 10.1.3 DMA Requests 10.1.2 Source and Destination Pointers10.1.4 External Requests Fetch Cycle 10.1.5 Internal Requests 10.1.5.1Timer 2-InitiatedTransfers10.1.7.2Software Termination 10.1.6 DMA Transfer CountsDIRECT MEMORY ACCESS UNIT 10.1.7.1Termination at Terminal Count10.1.8 DMA Unit Interrupts 10.1.9 DMA Cycles and the BIU10.1.10 The Two-ChannelDMA Unit Module 10.2.1 DMA Channel Parameters 10.2 PROGRAMMING THE DMA UNITDxSRCH Register Name:DMA Source Address Pointer HighRegister Mnemonic DxSRCL Register Name:DMA Source Address Pointer LowRegister Mnemonic Register Function DIRECT MEMORY ACCESS UNITRegister Mnemonic DxDSTHDxDSTL Register Name:DMA Destination Address Pointer LowRegister Mnemonic DIRECT MEMORY ACCESS UNIT DMA Control RegisterDxCON Controls DMA channel parametersRegister Mnemonic DIRECT MEMORY ACCESS UNITRegister Name DMA Control RegisterDxCON Register NameDMA Control Register Register Mnemonic10.2.1.6Programming the Transfer Count Options DIRECT MEMORY ACCESS UNIT10.2.1.4Arming the DMA Channel 10.2.1.5Selecting Channel SynchronizationRegister Name DMA Transfer CountDxTC Contains the DMA channel’s transfer count10.3.1 DRQ Pin Timing Requirements 10.2.2 Suspension of DMA Transfers10.2.3 Initializing the DMA Unit 10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT10.3.3 DMA Transfer Rates 10.3.2 DMA Latency10.4 DMA UNIT EXAMPLES 10.3.4 Generating a DMA AcknowledgeExample 10-1.Initializing the DMA Unit DIRECT MEMORY ACCESS UNITExample 10-1.Initializing the DMA Unit Continued DIRECT MEMORY ACCESS UNITDIRECT MEMORY ACCESS UNIT Example 10-1.Initializing the DMA Unit ContinuedSECTORS Example 10-2.Timed DMA Transfers DIRECT MEMORY ACCESS UNITExample 10-2.Timed DMA Transfers Continued DIRECT MEMORY ACCESS UNITPage Math Coprocessing Page CHAPTER MATH COPROCESSING 11.1 OVERVIEW OF MATH COPROCESSING11.2 AVAILABILITY OF MATH COPROCESSING 11.3.1 80C187 Instruction Set 11.3 THE 80C187 MATH COPROCESSOR•the 80C187 uses register or memory operands Division MATH COPROCESSINGTable 11-2.80C187 Arithmetic Instructions AdditionTable 11-4.80C187 Transcendental Instructions MATH COPROCESSING 11.3.1.3Comparison InstructionsTable 11-3.80C187 Comparison Instructions 11.3.1.4Transcendental InstructionsTable 11-6.80C187 Processor Control Instructions MATH COPROCESSING 11.3.1.5Constant InstructionsTable 11-5.80C187 Constant Instructions 11.3.1.6Processor Control Instructions11.4 MICROPROCESSOR AND COPROCESSOR OPERATION 11.3.2 80C187 Data TypesFigure 11-1. 80C187-SupportedData Types MATH COPROCESSINGCore MATH COPROCESSING80C187 ModularTable 11-7.80C187 I/O Port Assignments 11.4.2 Processor Bus Cycles Accessing the 80C18711.4.1 Clocking the 80C187 MATH COPROCESSING11.4.3 System Design Tips Core MATH COPROCESSING80C187 Modular11.5 EXAMPLE MATH COPROCESSOR ROUTINES 11.4.4 Exception Trapping80C187 MATH COPROCESSING80C186 Modular CoreMATH COPROCESSING MATH COPROCESSING ONCE Mode Page 12.1 ENTERING/LEAVING ONCE MODE CHAPTER ONCE MODENOTES: 1. Entering ONCE Mode 2.Latching ONCE Mode ONCE MODEFigure 12-1.Entering/Leaving ONCE Mode bidirectional weakly held pins except OSCOUT80C186 Instruction Set Additions and Extensions Page A.1 80C186 INSTRUCTION SET ADDITIONS A.1.1 Data Transfer InstructionsPUSHA/POPA A.1.3 High-LevelInstructions A.1.2 String InstructionsINS source_string, port OUTS port, destination_string1.Main has variables at fixed locations Figure A-2.Variable Access in Nested Procedures 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSFigure A-3.Stack Frame for Main at Level BP SP BPA = BP Value for Procedure AFigure A-4.Stack Frame for Procedure A at Level 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSDisplay B Dynamic Storage B 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSBP SP Old BP BPM BPM BPM BPA BPA BPM BPA BPB80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS LEAVEPUSH data BOUND register, addressA.2 80C186 INSTRUCTION SET ENHANCEMENTS A.2.1 Data Transfer InstructionsSAL destination, count A.2.2 Arithmetic InstructionsIMUL destination, source, data A.2.3 Bit Manipulation InstructionsRCR destination, count ROL destination, countROR destination, count RCL destination, countInput Synchronization Page APPENDIX B INPUT SYNCHRONIZATION B.1 WHY SYNCHRONIZERS ARE REQUIREDB.2 ASYNCHRONOUS PINS Instruction Set Descriptions Page Table C-1.Instruction Format Variables APPENDIX C INSTRUCTION SET DESCRIPTIONSDescription INSTRUCTION SET DESCRIPTIONSTable C-2.Instruction Operands OperandTable C-3.Flag Bit Functions INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set INSTRUCTION SET DESCRIPTIONSINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedADC dest, src Description INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameTable C-4.Instruction Set Continued Call ProcedureCALL procedure-name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSName Clear Interrupt-enableFlagINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedName INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-10INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-11 Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-12Table C-4.Instruction Set Continued When Source Operand is a ByteWhen Source Operand is a Word INSTRUCTION SET DESCRIPTIONSC-14 Procedure EntryINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedName INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-15Table C-4.Instruction Set Continued When Source Operand is a ByteWhen Source Operand is a Word INSTRUCTION SET DESCRIPTIONSIN accum, port INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-17Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-18Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-19JA disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-20JNB disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JAE disp8JZ disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JE disp8JGE disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JL disp8JNZ disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JNE disp8JP disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JO disp8LDS dest, src INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-26C-27 Load Pointer Using ESINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedLODS src-string INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-28MOV dest, src INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-29MOVS dest-string, src-string INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-30INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-31 Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-32Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-33INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-34 Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-35Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-36INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-37 Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-38Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-39SAL dest, count INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued SHL dest, countName INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-41Table C-4.Instruction Set Continued When Source Operand is a ByteWhen Source Operand is a Word INSTRUCTION SET DESCRIPTIONSSHR dest, src INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-43STOS dest-string INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-44Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-45Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-46Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-47Page Instruction Set Opcodes and Clock Cycles Page APPENDIX D INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-1.Operand Variables Format INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary FunctionARITHMETIC INSTRUCTIONS INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued DATA TRANSFER INSTRUCTIONS ContinuedINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedARITHMETIC INSTRUCTIONS Continued BIT MANIPULATION INSTRUCTIONS INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued ARITHMETIC INSTRUCTIONS ContinuedShifts/Rotates INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued BIT MANIPULATION INSTRUCTIONS ContinuedTable D-2.Instruction Set Summary Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESIteration Control INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued PROGRAM TRANSFER INSTRUCTIONS ContinuedByte INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued Table D-3.Machine Instruction Decoding GuideBytes 3–6 INSTRUCTION SET OPCODES AND CLOCK CYCLESByte ByteBytes 3–6 INSTRUCTION SET OPCODES AND CLOCK CYCLESByte ByteBytes 3–6 INSTRUCTION SET OPCODES AND CLOCK CYCLESByte ByteBytes 3–6 INSTRUCTION SET OPCODES AND CLOCK CYCLESByte ByteBytes 3–6 INSTRUCTION SET OPCODES AND CLOCK CYCLESByte ByteBytes 3–6 INSTRUCTION SET OPCODES AND CLOCK CYCLESByte ByteBytes 3–6 INSTRUCTION SET OPCODES AND CLOCK CYCLESByte ByteBytes 3–6 INSTRUCTION SET OPCODES AND CLOCK CYCLESByte ByteBytes 3–6 INSTRUCTION SET OPCODES AND CLOCK CYCLESByte ByteBytes 3–6 INSTRUCTION SET OPCODES AND CLOCK CYCLESByte ByteTable D-4.Mnemonic Encoding Matrix Left Half INSTRUCTION SET OPCODES AND CLOCK CYCLESINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4.Mnemonic Encoding Matrix Right HalfD-21 Abbr INSTRUCTION SET OPCODES AND CLOCK CYCLESAbbr DefinitionIndex Page ARDY, See READY Arithmetic INDEXINDEX Crystal‚ See OscillatorData bus, See Address and data bus Index-3 INDEXSee also Bus cycles See also Refresh Control UnitINDEX Index-4interrupt Index-5 INDEXIndex-6 INDEXTimers‚ See Timer Counter Unit TCU INDEXIndex-7 Index-8 INDEX