Intel 80C188XL, 80C186XL user manual 3.4.2Data Phase, 3.4.3Wait States

BUS INTERFACE UNIT

3.4.2Data Phase

Figure 3-12 shows the timing relationships for the data phase of a bus cycle. The only bus cycle type that does not have a data phase is a bus halt. During the data phase, the bus transfers infor- mation between the internal units and the memory or peripheral device selected during the ad- dress/status phase. Appropriate control signals become active to coordinate the transfer of data.

The data phase begins at phase 1 of T2 and continues until phase 2 of T4 or TI. The length of the data phase varies depending on the number of wait states. Wait states occur after T3 and before T4 or TI.

3.4.3Wait States

Wait states extend the data phase of the bus cycle. Memory and I/O devices that cannot provide or accept data in the minimum four CPU clocks require wait states. Figure 3-13 shows a typical bus cycle with wait states inserted.

The bus ready inputs (ARDY and SRDY) and the Chip-Select Unit control bus cycle wait states. Only the bus ready inputs are described in this chapter. (See Chapter 6, “Chip-Select Unit,” for additional information.)

Figure 3-14 shows a simplified block diagram of the ARDY and SRDY inputs. Either ARDY or SRDY active signals a bus ready condition; therefore, both pins must be inactive to signal a not- ready condition. Depending on the size and characteristics of the system, ready implementation can take one of two approaches: normally not-ready or normally ready.

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