Intel 80C186XL 8.4.5In-ServiceRegister, Register Name, Priority Mask Register, Register Mnemonic

INTERRUPT CONTROL UNIT

Register Name:				Priority Mask Register
Register Mnemonic:				PRIMSK
Register Function:				Masks lower-priority interrupt sources
15									0
							P	P	P
							M	M	M
							2	1	0
									A1216-A0
		Bit	Bit Name	Reset		Function
	Mnemonic			State
	PM2:0		Priority	111	Defines a priority-based interrupt mask.
			Mask		Interrupts whose priority is lower than this value
					are masked.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 8-9. Priority Mask Register

8.4.5In-Service Register

The In-Service register has a bit for each interrupt source. The bits indicate which source’s inter- rupt handlers are currently executing. The In-Service bit is set when an interrupt is acknowl- edged; the interrupt handler must clear it with an End-of-Interrupt (EOI) command. The Interrupt Control Unit uses the In-Service register to support interrupt nesting.

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