Cypress CY7C1347G Maximum Ratings, Electrical Characteristics, Operating Range, Vddq, Temperature

CY7C1347G

Maximum Ratings

Exceeding the maximum ratings may shorten the battery life of the device. User guidelines are not tested.

Storage Temperature		−65°C to +150°C
Ambient Temperature with
Power Applied		−55°C to +125°C
Supply Voltage on VDD Relative to GND	.........	−0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND		−0.5V to +VDD
DC Voltage Applied to Outputs
in High-Z State	−0.5V to VDD + 0.5V
DC Input Voltage	−0.5V to VDD + 0.5V

Electrical Characteristics

Over the Operating Range[8, 9]

Current into Outputs (LOW)			20 mA
Static Discharge Voltage			> 2001V
(MIL-STD-883, Method 3015)
Latch-Up Current	...................................................		> 200 mA
Operating Range
Range	Ambient	VDD	VDDQ
	Temperature
Commercial	0°C to +70°C	3.3V	2.5V −5%
		−5%/+10%	to VDD
Industrial	–40°C to +85°C

Parameter	Description	Test Conditions		Min	Max	Unit
VDD	Power Supply Voltage			3.135	3.6	V
VDDQ	IO Supply Voltage			2.375	VDD	V
VOH	Output HIGH Voltage	For 3.3V IO, IOH = –4.0 mA		2.4		V
		For 2.5V IO, IOH = –1.0 mA		2.0		V
VOL	Output LOW Voltage	For 3.3V IO, IOL = 8.0 mA			0.4	V
		For 2.5V IO, IOL = 1.0 mA			0.4	V
VIH	Input HIGH Voltage[8]	For 3.3V IO		2.0	VDD + 0.3V	V
		For 2.5V IO		1.7	VDD + 0.3V	V
VIL	Input LOW Voltage[8]	For 3.3V IO		–0.3	0.8	V
		For 2.5V IO		–0.3	0.7	V
IX	Input Leakage Current	GND < VI < VDDQ		−5	5	μA
	Except ZZ and MODE
	Input Current of MODE	Input = VSS		−30		μA
		Input = VDD			5	μA
	Input Current of ZZ	Input = VSS		−5		μA
		Input = VDD			30	μA
IOZ	Output Leakage Current	GND ≤ VI ≤ VDDQ, Output Disabled		−5	5	μA
IDD	VDD Operating Supply	VDD = Max., IOUT = 0 mA,	4 ns cycle, 250 MHz		325	mA
	Current	f = fMAX = 1/tCYC
			5 ns cycle, 200 MHz		265	mA
			6 ns cycle, 166 MHz		240	mA
			7.5 ns cycle, 133 MHz		225	mA
ISB1	Automatic CE	Max. VDD, Device Deselected,	4 ns cycle, 250 MHz		120	mA
	Power Down	VIN > VIH or VIN < VIL
			5 ns cycle, 200 MHz		110	mA
	Current—TTL Inputs	f = fMAX = 1/tCYC
			6 ns cycle, 166 MHz		100	mA
			7.5 ns cycle, 133 MHz		90	mA
ISB2	Automatic CE	Max. VDD, Device Deselected,	All speeds		40	mA
	Power Down	VIN < 0.3V or VIN > VDDQ – 0.3V,
	Current—CMOS Inputs	f = 0

Notes

8.Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2V (pulse width less than tCYC/2).

9.TPower up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

Document #: 38-05516 Rev. *F Page 9 of 22

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