Cypress CY7C1347G manual Switching Characteristics

																	CY7C1347G
Switching Characteristics
Over the Operating Range[14, 15]
Parameter									Description		–250		–200		–166		–133		Unit
											Min	Max	Min	Max	Min	Max	Min	Max
tPOWER	V (Typical) to the first Access[10]										1		1		1		1		ms
	DD
Clock
tCYC	Clock Cycle Time										4.0		5.0		6.0		7.5		ns
tCH	Clock HIGH										1.7		2.0		2.5		3.0		ns
tCL	Clock LOW										1.7		2.0		2.5		3.0		ns
Output Times
tCO	Data Output Valid After CLK Rise											2.6		2.8		3.5		4.0	ns
tDOH	Data Output Hold After CLK Rise										1.0		1.0		1.5		1.5		ns
tCLZ	Clock to Low-Z[11, 12, 13]										0		0		0		0		ns
tCHZ	Clock to High-Z[11, 12, 13]											2.6		2.8		3.5		4.0	ns
tOEV		LOW to Output Valid										2.6		2.8		3.5		4.5	ns
	OE
tOELZ		LOW to Output Low-Z[11, 12, 13]									0		0		0		0		ns
	OE
tOEHZ		HIGH to Output High-Z[11, 12, 13]										2.6		2.8		3.5		4.0	ns
	OE
Setup Times
tAS	Address Setup Before CLK Rise										1.2		1.2		1.5		1.5		ns
tADS									Setup Before CLK Rise		1.2		1.2		1.5		1.5		ns
	ADSC,					ADSP
tADVS				Setup Before CLK Rise							1.2		1.2		1.5		1.5		ns
	ADV
tWES										Setup Before CLK Rise	1.2		1.2		1.5		1.5		ns
	GW,			BWE,			BW
										X
tDS	Data Input Setup Before CLK Rise										1.2		1.2		1.5		1.5		ns
tCES	Chip Enable Setup Before CLK Rise										1.2		1.2		1.5		1.5		ns
Hold Times
tAH	Address Hold After CLK Rise										0.3		0.5		0.5		0.5		ns
tADH								Hold After CLK Rise			0.3		0.5		0.5		0.5		ns
	ADSP,				ADSC
tADVH			Hold After CLK Rise								0.3		0.5		0.5		0.5		ns
	ADV
tWEH										Hold After CLK Rise	0.3		0.5		0.5		0.5		ns
	GW,			BWE,			BW
										X
tDH	Data Input Hold After CLK Rise										0.3		0.5		0.5		0.5		ns
tCEH	Chip Enable Hold After CLK Rise										0.3		0.5		0.5		0.5		ns

Notes

10.This part has an internal voltage regulator; tPOWER is the time that the power must be supplied above VDD(min) initially before a read or write operation can be initiated.

11.tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 10. Transition is measured ±200 mV from steady-state voltage.

12.At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z before Low-Z under the same system conditions.

13.This parameter is sampled and not 100% tested.

14.Timing references level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V on all data sheets.

15.Test conditions shown in (a) of AC Test Loads and Waveforms on page 10 unless otherwise noted.

Document #: 38-05516 Rev. *F Page 11 of 22

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