Ordering Information | Cypress CY7C1347G instruction

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Cypress CY7C1347G manual Ordering Information

Contents

Features CY7C1347GSelection Guide Functional Description1 Block Diagram ADDRESSREGISTER ADSC Pinouts CY7C1347G CY7C1347G CY7C1347G Table 1. Pin DefinitionsName Description Single Read Accesses Single Write Accesses Initiated by ADSPSingle Write Accesses Initiated by ADSC Functional Overview 2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW Table 5. Truth Table 2, 3, 4, 5 Electrical Characteristics Maximum RatingsOperating Range VDDQ Electrical Characteristics continued CapacitanceThermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Figure 5. Read Cycle Timing16 Switching Waveforms continued Figure 6. Write Cycle Timing16 Page 14 of Figure 7. Read/Write Cycle Timing16, 1819. GW is HIGH 21. DQs are in high-Z when exiting ZZ sleep mode ALL INPUTS except ZZ Ordering Information Ordering Information continued Package Diagrams Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams continued Figure 10. 119-Ball BGA 14 x 22 x 2.4 mm Figure 11. 165-Ball FBGA 13 x 15 x 1.4 mm PACKAGE WEIGHT 0.475gPage 20 of Document History Page Document Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAMDocument Number Submission Sales, Solutions, and Legal Information PSoC SolutionsWorldwide Sales and Design Support Products