CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Document #: 38-05357 Rev. *G Page 24 of 31
Figure 5. Read/Write Cycle Timing[24, 26, 27]
.
Timing Diagrams (continued)
t
CYC
tCL
CLK
tADH
tADS
ADDRESS
tCH
tAH
tAS
A2
tCEH
tCES
Single WRITE
D(A3)
A3 A4
BURST READ
Back-to-Back READs
High-Z
Q(A2) Q(A4) Q(A4+1)
Q(A4+2)
Q(A4+3)
tWEH
tWES
tOEHZ
tDH
tDS
tCDV
tOELZ
A1 A5 A6
D(A5) D(A6)
Q(A1)
Back-to-Back
WRITEs
DON’T CARE UNDEFINED
ADSP
ADSC
BWE, BW X
CE
ADV
OE
Data In (D)
D
ata Out (Q)

Note

26.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

27.GW is HIGH

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