Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress CY7C1441AV33, CY7C1443AV33, CY7C1447AV33 manual Read/Write Cycle Timing24, 26

Models: CY7C1441AV33 CY7C1443AV33 CY7C1447AV33

1 31

Download 31 pages 10.77 Kb

Page 24

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Timing Diagrams (continued)

Figure 5. Read/Write Cycle Timing[24, 26, 27]

			tCYC
CLK		tCH	tCL
		tCH	tCL
	tADS	tADH
ADSP
ADSC
	tAS	tAH
ADDRESS	A1	A2	A3	A4
			tWES	t WEH

BWE, BW X

	tCES tCEH
CE
ADV
OE
			tDS tDH
Data In (D)	High-Z	t	D(A3)
		OEHZ
Data Out (Q)	Q(A1)	Q(A2)
	Back-to-Back READs		Single WRITE

tOELZ

tCDV
Q(A4)	Q(A4+1)	Q(A4+2)	Q(A4+3)
	BURST READ

DON’T CARE

UNDEFINED

A5A6

D(A5) D(A6)

Back-to-Back

WRITEs

.

Note

26.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

27.GW is HIGH

Document #: 38-05357 Rev. *G

Page 24 of 31

[+] Feedback

Image 24

Cypress CY7C1441AV33, CY7C1443AV33, CY7C1447AV33 manual Read/Write Cycle Timing24, 26

Contents

Features Selection Guide Functional DescriptionDescription 133 MHz 100 MHz Unit Cypress Semiconductor Corporation 198 Champion Court Logic Block Diagram CY7C1441AV33 1M x Logic Block Diagram CY7C1443AV33 2Mx Logic Block Diagram CY7C1447AV33 512K x BWE Enable CE1 Register CE2 CE3 Pin Configurations CY7C1441AV33CY7C1443AV33 2M x TDI TDO Mode BWE Adsc ADVAdsp DQP C DQ G DQ B DQ GDQ B DQP G DQP C DQP DQ C Pin Definitions Name DescriptionByte Write Select Inputs, Active LOW. Qualified with Power Supply Inputs to the Core of the Device Power Supply for the IO CircuitryGround for the Core of the Device Ground for the IO Circuitry Interleaved Burst Address Table Mode = Floating or VDD Functional OverviewLinear Burst Address Table ZZ Mode Electrical Characteristics Truth TableParameter Description Test Conditions Min Max Unit Cycle Description Partial Truth Table for Read/Write Truth Table for Read/WriteFunction CY7C1441AV33 2 Function CY7C1443AV33 TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Instruction Register TAP Timing Extest TAP AC Switching Characteristics Setup TimesParameter Description Min Max Unit Clock Hold Times TAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Parameter Description Conditions Min Max Unit Identification Register Definitions Scan Register SizesIdentification Codes Register Name Bit Size Ball Fbga Boundary Scan Order13,14 CY7C1441AV33 1M x 36, CY7C1443AV33 2M x Bit # Ball IDBit # Ball ID Electrical Characteristics Over the Operating Range15 DC Electrical Characteristics Over the Operating RangeMaximum Ratings Operating Range Capacitance Thermal Resistance Switching Characteristics 100 Unit Parameter Min MaxOutput Times Timing Diagrams Adsp AdscData Out Q High-Z QA1 ADV suspends burst Write Cycle Timing24 Read/Write Cycle Timing24, 26 ZZ Mode Timing28 Ordering Information Package Diagrams Pin Tqfp 14 x 20 x 1.4 mm Ball Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x1.76 mm Issue Date Orig. Description of Change CJMSYT RXU VKNVKN/AESA