Cypress CY7C1447AV33 Power Supply Inputs to the Core of the Device, Ground for the IO Circuitry

			CY7C1441AV33
			CY7C1443AV33,CY7C1447AV33
Pin Definitions (continued)
Name		IO	Description
DQs		IO-	Bidirectional Data IO lines. As inputs, they feed into an on-chip data register
	Synchronous		that is triggered by the rising edge of CLK. As outputs, they deliver the data
			contained in the memory location specified by the addresses presented during
			the previous clock rise of the read cycle. The direction of the pins is controlled
			by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,
			DQs and DQPX are placed in a tri-state condition.The outputs are automati-
			cally tri-stated during the data portion of a write sequence, during the first clock
			when emerging from a deselected state, and when the device is deselected,
			regardless of the state of OE.
DQPX		IO-	Bidirectional Data Parity IO Lines. Functionally, these signals are identical
	Synchronous		to DQs. During write sequences, DQPx is controlled by BW[A:H] correspond-
			ingly.
MODE	Input-Static		Selects Burst Order. When tied to GND selects linear burst sequence. When
			tied to VDD or left floating selects interleaved burst sequence. This is a strap
			pin and should remain static during device operation. Mode Pin has an internal
			pull up.
VDD	Power Supply		Power Supply Inputs to the Core of the Device.
VDDQ	IO Power Supply		Power Supply for the IO Circuitry.
VSS	Ground		Ground for the Core of the Device.
VSSQ	IO Ground		Ground for the IO Circuitry.
TDO	JTAG serial output		Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of
	Synchronous		TCK. If the JTAG feature is not being utilized, this pin should be left uncon-
			nected. This pin is not available on TQFP packages.
TDI	JTAG serial		Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If
		input	the JTAG feature is not being utilized, this pin can be left floating or connected
	Synchronous		to VDD through a pull up resistor. This pin is not available on TQFP packages.
TMS	JTAG serial		Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If
		input	the JTAG feature is not being utilized, this pin can be disconnected or
	Synchronous		connected to VDD. This pin is not available on TQFP packages.
TCK	JTAG-Clock		Clock Input to the JTAG Circuitry. If the JTAG feature is not being utilized,
			this pin must be connected to VSS. This pin is not available on TQFP
			packages.
NC	-		No Connects. Not internally connected to the die. 72M, 144M and 288M are
			address expansion pins are not internally connected to the die.
NC/72M, NC/144M,	-		No Connects. Not internally connected to the die. NC/72M, NC/144M,
NC/288M, NC/576M			NC/288M, NC/576M and NC/1G are address expansion pins are not internally
NC/1G			connected to the die.

Document #: 38-05357 Rev. *G Page 8 of 31

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