Cypress CY7C1447AV33, CY7C1441AV33, CY7C1443AV33 manual TAP Timing, Extest

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

EXTEST

The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the shift-DR controller state.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #89 (for 165-FBGA package) or bit #138 (for 209-FBGA package). When this scan cell, called the “extest output bus tri-state”, is latched into the preload register during the “Update-DR” state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current

instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

1	2
Test Clock
(TCK)	tTH
tTMSS	tTMSH

Test Mode Select (TMS)

tTDIS tTDIH

Test Data-In (TDI)

3	4	5	6
tTL	tCYC

tTDOV

tTDOX

Test Data-Out (TDO)

DON’T CARE

UNDEFINED

Document #: 38-05357 Rev. *G Page 14 of 31

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