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Cypress CY7C1441AV33, CY7C1443AV33, CY7C1447AV33 manual Package Diagrams, Pin Tqfp 14 x 20 x 1.4 mm

Models: CY7C1441AV33 CY7C1443AV33 CY7C1447AV33

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Package Diagrams

Figure 1. 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

14.00±0.10

100

22.00±0.20

20.00±0.10

0.30±0.08

0.65

TYP.

12° ±1° (8X)

1.40±0.05

SEE DETAIL

0.20 MAX.

1.60 MAX.

R 0.08 MIN. 0.20 MAX.

0.25

0° MIN.

STAND-OFF 0.05 MIN. 0.15 MAX.

SEATING PLANE

NOTE:

0.10

GAUGE PLANE

0° -7°

0.60±0.15

1.00 REF.

R 0.08 MIN. 0.20 MAX.

0.20 MIN.

DETAIL A

1.JEDEC STD REF MS-026

2.BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3.DIMENSIONS IN MILLIMETERS

51-85050-*B

Document #: 38-05357 Rev. *G

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Cypress CY7C1441AV33, CY7C1443AV33, CY7C1447AV33 manual Package Diagrams, Pin Tqfp 14 x 20 x 1.4 mm

Contents

Cypress Semiconductor Corporation 198 Champion Court FeaturesSelection Guide Functional Description Description 133 MHz 100 MHz Unit Logic Block Diagram CY7C1443AV33 2Mx Logic Block Diagram CY7C1441AV33 1M x BWE Enable CE1 Register CE2 CE3 Logic Block Diagram CY7C1447AV33 512K x Pin Configurations CY7C1441AV33CY7C1443AV33 2M x DQP C TDI TDO ModeBWE Adsc ADV Adsp DQP DQ C DQ G DQ BDQ G DQ B DQP G DQP C Pin Definitions Name DescriptionByte Write Select Inputs, Active LOW. Qualified with Ground for the IO Circuitry Power Supply Inputs to the Core of the DevicePower Supply for the IO Circuitry Ground for the Core of the Device Interleaved Burst Address Table Mode = Floating or VDD Functional OverviewLinear Burst Address Table Cycle Description ZZ Mode Electrical CharacteristicsTruth Table Parameter Description Test Conditions Min Max Unit Function CY7C1443AV33 Partial Truth Table for Read/WriteTruth Table for Read/Write Function CY7C1441AV33 2 Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State Diagram Instruction Register TAP Instruction Set Extest TAP Timing Hold Times TAP AC Switching CharacteristicsSetup Times Parameter Description Min Max Unit Clock Parameter Description Conditions Min Max Unit TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test Conditions Register Name Bit Size Identification Register DefinitionsScan Register Sizes Identification Codes Ball Fbga Boundary Scan Order13,14 CY7C1441AV33 1M x 36, CY7C1443AV33 2M x Bit # Ball IDBit # Ball ID Operating Range Electrical Characteristics Over the Operating Range15DC Electrical Characteristics Over the Operating Range Maximum Ratings Thermal Resistance Capacitance Switching Characteristics 100 Unit Parameter Min MaxOutput Times ADV suspends burst Timing DiagramsAdsp Adsc Data Out Q High-Z QA1 Write Cycle Timing24 Read/Write Cycle Timing24, 26 ZZ Mode Timing28 Ordering Information Pin Tqfp 14 x 20 x 1.4 mm Package Diagrams Ball Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x1.76 mm Issue Date Orig. Description of Change CJMSYT RXU VKNVKN/AESA