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Cypress CY7C1441AV33, CY7C1443AV33, CY7C1447AV33 Figure 4. Write Cycle Timing[24, 25]

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Document #: 38-05357 Rev. *G Page 23 of 31

Figure 4. Write Cycle Timing[24, 25]

Timing Diagrams (continued)

tCYC

tCL

CLK

tADH

tADS

ADDRESS

tCH

tAH

tAS

tCEH

tCES

High-Z

BURST READ BURST WRITE

D(A2)

D(A2 + 1)

D(A1) D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

tOEHZ

tADVH

tADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are ignored for rst cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

ADSP

ADSC

BWE,

ADV

Data in (D)

ata Out (Q)

Note

25.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW

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Contents

Main 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Features Functional Description Selection Guide Logic Block Diagram CY7C1441AV33 (1M x 36) Logic Block Diagram CY7C1443AV33 (2Mx 18) CE ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 3 of 31 Logic Block Diagram CY7C1447AV33 (512K x 72) BYTE MODE CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Pin Configurations Figure 1. 100-Pin TQFP Pinout CY7C1441AV33 (1Mx 36) CY7C1443AV33 (2M x 18) Pin Configurations 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1441AV33 (1M x 36) CY7C1443AV33 (2M x 18) 2345671 A B C D E F G H J K L M N P R 891011 Pin Configurations 209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1447AV33 (512K 72) CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Pin Definitions Functional Overview Single Read Accesses Single Write Accesses Initiated by ADSP Single Write Accesses Initiated by ADSC Burst Sequences ZZ Mode Electrical Characteristics Truth Table Partial Truth Table for Read/Write Truth Table for Read/Write IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access Port (TAP) Performing a TAP Reset TAP Registers TAP Instruction Set CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 TAP Ti min g TAP AC Switching Characteristics 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions 50 DO T Identification Register Definitions Scan Register Sizes Identification Codes 165-ball FBGA Boundary Scan Order Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit Capacitance Thermal Resistance Switching Characteristics Timing Diagrams Figure 3. Read Cycle Timing Figure 4. Write Cycle Timing[24, 25] Figure 5. Read/Write Cycle Timing Figure 6. ZZ Mode Timing Ordering Information Package Diagrams Figure 1. 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050) A Figure 2. 165-ball FBGA (15 x 17 x 1.4 mm) (51-85165) Package Diagrams 51-85165-*A Page Document History Page