dCS 954 User Manual

Manual for Standard Software Version 1.5x

dCS Ltd

June 2000

 

 

Clocking

The sample clock quality significantly determines the performance of a DAC.

The highest quality clocks that are available are crystals, so we use these. The dCS 954 uses one of two on-board voltage controlled crystal oscillators (VCXOs) as a clock source – one for 48 kS/s related outputs and one for 44.1 kS/s related outputs. When the unit is slaved to an external source, the appropriate VCXO is selected and synchronised to this by a phase locked loop (PLL). The PLL is of a special narrow bandwidth type, that provides a high degree of "clock cleaning" - but even so, signal quality may degrade if particularly poor source clocks are used. A consequence of the narrow bandwidth is that it takes quite a long time for the PLL to lock to a new clock frequency – of the order of 2 seconds. The PLL uses DSP assistance to keep this time acceptable.

Synchronising to source

 

Pull in range

> ± 300 ppm about nominal frequency

Lock in time

< 2 seconds for most situations

The PLL is very robust, and will lock to very poor signals if necessary. Data is decoded using a much wider band (faster) PLL, so AES3 type low frequency jitter on the input clock can be handled, and will be cleaned.

If you need to synchronise several items of digital equipment, we recommend using a dCS 992 Master Clock.

There is a further discussion of some types of timing error in section “Jitter and PLL bandwidths” on page 68.

Manual part no: DOC136954 iss 2B1

Page 39

file 135954ma2b1.pdf available from website

Contact dCS on + 44 1799 531 999

email to: more@dcsltd.co.uk

(inside the UK replace + 44 with 0)

web site: www.dcsltd.co.uk