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Base + 7 | Write |
| D/A Channel and Control Register |
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Bit No. |
| 7 | 6 |
| 5 | 4 | 3 | 2 | 1 | 0 |
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Name |
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| DAUPDT | DACH2 | DACH1 | DACH0 |
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DAUPDT | Writing a 1 to this bit updates the D/A chip. All channels with new data written to | |||||||||
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| them since the previous update are updated simultaneously. When a 1 is written | ||||||||
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| to this bit the other bits in the register are ignored. |
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When DAUPDT = 0, the remaining bits in this register behave as described below:
Base + 7 | Read | Optocoupler Input Port and Edge Detection Register |
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Bit No. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Name | OEDGE3 | OEDGE2 | OEDGE1 | OEDGE0 | OPTO3 | OPTO2 | OPTO1 | OPTO0 |
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0 edge has not occurred since last flip flop reset
These bits are reset when this register is read or when the digital input interrupt flip flop is reset by writing to the CLRO bit in register 8.
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