Digital I/O Operation | Diamond Power Products MM-48-AT specification

13. DIGITAL I/O OPERATION

Diamond-MM-48-AT contains a 4-bit digital I/O port with programmable direction and edge detection capability. The digital I/O lines are located at pins 35 through 38 on the I/O header J3. They are CMOS / TTL compatible. Each line can drive up to -6mA in a logic high state or sink up to 8mA in a logic low state. All digital input lines have 10KΩ pull-up resistors. The I/O lines are written and read with 4 bits in the register at Base + 5.

To use the digital I/O lines for simple I/O, set the desired direction using the control register in Base + 4. Each bit’s direction may be set independently with the control bits DIR3-0 in this register. On power-up or system reset, all lines are set to input mode.

To enable edge detection, set the DINTE bit in Base + 11. When DINTE = 1, any change of state on any input line will generate an interrupt and set the DINT bit in Base + 11. The interrupt routine reads the data by reading from Base + 5, and then it clears the interrupt request by writing a 1 to the CLRD bit in Base + 11. When DINTE = 0, any pending interrupt request will be cleared, and further changes in state on the input lines will not generate interrupts.

NOTE: Diamond-MM-48-AT has 4 distinct interrupt circuits that may request interrupt service independently of each other. A PC/104 bus interrupt request will occur when any one of the circuits requests service. As long as any circuit is still requesting service, the interrupt request will stay active. This means that writing to the CLRD bit may not clear the bus interrupt request even though it clears the specific digital input interrupt request. The interrupt service routine is responsible for determining which of the three circuits is requesting service and handling all of them as needed.

Diamond-MM-48-AT User Manual V1.01

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Diamond Power Products MM-48-AT user manual Digital I/O Operation

Contents

DIAMOND-MM-48-AT Table of Contents Description DIAMOND-MM-48-AT Board Drawing O Header Pinout and PIN Description Signal Name DefinitionJ3 Analog and Digital I/O J4 Relays and Optocouplers Signal Name Definition Relay output contactsOptoisolated input contacts Base Address Board ConfigurationBase Address Jumper Position Hex Decimal Interrupt Level Selection Reserved Optocoupler PolarityAnalog Input Range Base + Write Function Read Function OverviewLSB MSB Write operations Register Map Bit AssignmentsDA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Read operations Base + Write Register DefinitionsDefinitions Base + Read Base + Read/Write A/D Channel Register AD9 AD8HIGH3 HIGH2 HIGH1 HIGH0 LOW3 LOW2 LOW1 LOW0 Base + Read/Write Relay Control Port Base + Read/Write Digital I/O Configuration RegisterRELAY7 RELAY6 RELAY5 RELAY4 RELAY3 RELAY2 RELAY1 RELAY0 DIR3 DIR2 DIR1 DIR0 Base + Read Digital I/O Data and Edge Status DIO3 DIO2 DIO1 DIO0DEDGE3 DEDGE2 DEDGE1 DEDGE0 DIO3 DIO2 DIO1 DIO0 OEN3 OEN2 OEN1 OEN0 POL3 POL2 POL1 POL0 Daupdt DACH2 DACH1 DACH0 Base + Write Channel and Control RegisterOEDGE3 OEDGE2 OEDGE1 OEDGE0 OPTO3 OPTO2 OPTO1 OPTO0 Dapre Daprld Reset Fiforst Adstart Base + Write Command Register POL ADCH3 ADCH2 ADCH1 ADCH0 Base + Read Status Register CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken Clksel Base + Write Configuration Register Adbusy Dabusy CKSEL1 CKFRQ1 CKFRQ0 Scnint Clken Clksel Base + Read Configuration & Status Register Fifoth Fifoen Scanen Base + Write Fifo Control RegisterBase + Read Fifo Status Register OVF Fifoth Fifoen Scanen Clrt Clrd Clro Clra Tinte Dinte Ointe Ainte Base + Write Interrupt Control Register Tint Dint Oint Aint Tinte Dinte Ointe Ainte Base + Read Interrupt Status Register Base + Read/Write Counter/Timer D15 Base + Read/Write Counter/Timer D7Base + Read/Write Counter/Timer D23 Ctrno Latch Gtdis Gten Ctdis Cten Load CLR Base + Write Counter/Timer Control RegisterCtrno Base + Read/Write Eeprom / TrimDAC Address Register Base + Read/Write Eeprom / TrimDAC Data Register Base + Write Calibration Control Register Base + Write Eeprom Access Key RegisterBase + Read Calibration Status Register Base + Read Fpga Revision Code Resolution Analog Input Ranges and ResolutionInput Ranges Single Ended and Differential Inputs Performing AN A/D Conversion LSB = readbase MSB = readbase+1 Data = MSB * 256 + LSB Trigger an A/D conversion on the current channel Input voltage = A/D value / 32768 * Full-scale voltage Trigger D SCAN, FIFO, and Interrupt OperationClken Clksel Conversion or Scan Interrupt Operation Fifo OperationFifoen Fifoth Scanen Fifoen = Operation Table Guidelines for Selecting Fifo Use Fifoen and FifothAinte Fifoen Scanen Analog Output Overview Generating AN Analog Output Reference Voltages Autocalibration Operation12.2 A/D calibration 12.3 D/A Calibration Digital I/O Operation Optocoupler Operation Procedure for enabling interrupts on selected edges Polarity and logic readback Edge detection assumes OENn = 1 to enable edge detection Relay Operation Counter 0 A/D Sample Control COUNTER/TIMER OperationCounter 1 Counting/Totalizing Functions Counter Command Sequences Counter Outpbase+15,0x01 Outpbase+15,0x81 Autocalibration SpecificationsGeneral