Epson S1C6200A, S1C6200 2.1.1 Program counter block, 2.1.2 Flags

2 MEMORY AND OPERATIONS

2.1.1 Program counter block

The program counter is used to point to the next instruction step to be executed by the CPU. See Figure 2.1.1.1.

The program counter has the following registers.

Table 2.1.1.1 Program counter registers

Register	Size
PCB (Program Counter-Bank)	1-bit register
PCP (Program Counter-Page)	4-bit counter
PCS (Program Counter-Step)	8-bit counter
NBP (New Bank Pointer)	1-bit register
NPP (New Page Pointer)	4-bit register

Program memory

(8,192 12-bit words max.)

Address decoder

PCB	PCP	PCS
(1)	(4)	(8)

NBPNPP

(1)(4)

Program counter block

Fig. 2.1.1.1 Program counter configuration

PCB, PCP and PCS together from a 13-bit counter which can address any location in program memory.

PCP and PCS together from a 12-bit counter which can address any location within a given bank of program memory. Each time an instruction other than a jump is executed, this counter increments by one. Thus, a jump instruction does not need to be executed between the last step of one page and the first step of the next.

The contents of NBP and NPP are loaded into PCB and PCP each time an instruction is executed. On reset, NBP and NPP are loaded with the same values as PCB and PCP.

2.1.2 Flags

The following flags are provided.

	Table 2.1.2.1		Flags
Flag		Menus		Size
Interrupt		I		1: Enabled
				0: Disabled
Decimal mode		D		1: Decimal
				0: Hexadecimal
Zero		Z		1: Set
				0: Ignored
Carry		C		1: Set
				0: Ignored

4 EPSON S1C6200/6200A CORE CPU MANUAL