Epson S1C6200A, S1C6200 2.2 Data Memory, 2.2.1 Data memory addressing, •Index register, (within page), only, (page specification), 4-bitdata, Register area

2 MEMORY AND OPERATIONS

2.2 Data Memory

The data memory area comprises 4,096 4-bit words. The RAM, timer, I/O and other peripheral circuits are mapped into this memory according to the designer's specifications. Figure 2.2.1 shows the data memory configuration.

								Page 15
							Page	14
							Step	0
	RP						Step	1		XHL or YHL
	Page 0									(within page)
					Page 3
	only
				Page	2
			Page 1
							Step	254
		Page	0				Step 255
		Step	0
		Step	1
SP									XP or YP
		Step	15						(page specification)
Page 0											Memory or I/O
only
		Step	254			4-bit data					Register area
		Step	255

Fig. 2.2.1 Data memory configuration

2.2.1 Data memory addressing

The following registers and pointers, which are described in detail below, are used to address the data memory.

Table 2.2.1.1 Registers and pointer for data memory addressing

Register/Pointer	Mnemonic	Size (bits)
Index Register X	IX	12
Index Register Y	IY	12
Stack Pointer	SP	8
Register	RP	4

•Index register IX

Index register IX has a 4-bit page part (XP) and an 8- bit register (XHL), and can address any location in the data memory. See Figure 2.2.1.1.

MSB LSB

4 4 4

XP XH XL

XHL is divided into two 4-bit groups: the four high-			XHL
		IX
order bits (XH) and the four low-order bits (XL), and
can address any location within a page.	Fig. 2.2.1.1 The configuration of the index register IX

–MX is the data memory location whose address is specified by IX.

–M(X) refers to the contents of the data memory location whose address is specified by IX.

–XHL can be incremented by 1 or 2 using a post-increment instruction (LDPX, ACPX, SCPX, LBPX or RETD). An overflow occurring in XHL does not affect the flags.

8 EPSON S1C6200/6200A CORE CPU MANUAL