Epson S1C6200A, S1C6200 A1 Outline of Differences, A2 Detailed Description of the Differences, A2.1 Initial reset, A2.2 Interrupt, Operation during interrupt issuance

APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU

APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU

S1C6200A is an improved version of the S1C6200. In this section, S1C6200A is described only in terms of its differences with S1C6200. It is recommended that users of S1C6200A read this section.

S1C6200A is a Core CPU which has been made easier to integrate software by improving the parts of the S1C6200 CPU which are difficult to use.

This section lists its differences with S1C6200; for items which are not included here, refer to the corresponding section in this manual.

A1 Outline of Differences

•The D (decimal) flag is set to "0" during initial reset.

•Modifications of the interrupt circuit

-The interrupt timing has been shifted to 0.5 clock later.

-<Reference> In the 1-chip micro controller which uses S1C6200A, writing on the interrupt mask register and reading the interrupt factor flag during EI (enable interrupt flag) are possible. (However, consult the respective hardware manuals to find out whether these are possible with the CPU peripheral circuits.)

A2 Detailed Description of the Differences

A2.1 Initial reset

The D (decimal) flag will be set as follows through initial reset:

Table A2.1.1 D (decimal) flag initial setting

CPU Core	S1C6200A	S1C6200
D (decimal) flag setting	0	Undefined

Owing to this, bugs due to omission of D (decimal) flag setting during software development can now be easily prevented.

For the values of other registers and flags during initial reset, see Section 2.5.4, "Initial reset".

A2.2 Interrupt

Operation during interrupt issuance

The time it takes to complete interrupt processing by hardware after the Core CPU receives the interrupt request has changed as follows:

Table A2.2.1 Required interrupt processing time

Item		S1C6200A	S1C6200
Item		(clock cycles)	(clock cycles)
		(clock cycles)	(clock cycles)

a) During instruction execution	12-cycle instruction execution	12.5 to 24.5	13 to 25

	7-cycle instruction execution	12.5 to 19.5	13 to 20

	5-cycle instruction execution	12.5 to 17.5	13 to 18

b) At HALT mode		14 to 15	14 to 15

c) During PSET instruction execution	PSET + CALL	12.5 to 24.5	13 to 25

	PSET + JP	12.5 to 22.5	13 to 23

Figure A2.2.1 shows the timing chart of the S1C6200A interrupt.

EPSON

S1C6200/6200A CORE CPU MANUAL