Epson S1C6200A, S1C6200 25

3 INSTRUCTION SET

Classification	Mne-	Operand					Operation Code									Flag		Clock							Operation
Classification	monic	Operand	B A 9 8				7 6 5 4				3 2 1 0				I D Z		C	Clock							Operation
	monic

Stack	POP	YH	1	1	1	1	1	1	0	1	1	0	0	0				5	YH ←				M(SP), SP ←		SP+1

operation		YL	1	1	1	1	1	1	0	1	1	0	0	1				5	YL ←			M(SP), SP ←			SP+1

instructions		F	1	1	1	1	1	1	0	1	1	0	1	0	↓↑	↓↑ ↑ ↓	↓↑	5	F ←	M(SP), SP ←					SP+1

	LD	SPH, r	1	1	1	1	1	1	1	0	0	0	r1	r0				5	SPH ←				r

		SPL, r	1	1	1	1	1	1	1	1	0	0	r1	r0				5	SPL ←				r

		r, SPH	1	1	1	1	1	1	1	0	0	1	r1	r0				5	r ←	SPH

		r, SPL	1	1	1	1	1	1	1	1	0	1	r1	r0				5	r ←	SPL

Arithmetic	ADD	r, i	1	1	0	0	0	0	r1	r0	i3	i2	i1	i0		★ ↓↑	↓↑	7	r ←	r+i3~i0

instructions		r, q	1	0	1	0	1	0	0	0	r1	r0	q1 q0			★ ↓↑	↓↑	7	r ←	r+q

	ADC	r, i	1	1	0	0	0	1	r1	r0	i3	i2	i1	i0		★ ↓↑	↓↑	7	r ←	r+i3~i0+C

		r, q	1	0	1	0	1	0	0	1	r1	r0	q1 q0			★ ↓↑	↓↑	7	r ←	r+q+C

	SUB	r, q	1	0	1	0	1	0	1	0	r1	r0	q1 q0			★ ↓↑	↓↑	7	r ←	r-q

	SBC	r, i	1	1	0	1	0	1	r1	r0	i3	i2	i1	i0		★ ↓↑	↓↑	7	r ←	r-i3~i0-C

		r, q	1	0	1	0	1	0	1	1	r1	r0 q1 q0				★ ↓↑	↓↑	7	r ←	r-q-C

	AND	r, i	1	1	0	0	1	0	r1	r0	i3	i2	i1	i0		↓↑		7	r ←	rΛ		i3~i0

		r, q	1	0	1	0	1	1	0	0	r1	r0 q1 q0				↓↑		7	r ←	rΛ q

	OR	r, i	1	1	0	0	1	1	r1	r0	i3	i2	i1	i0		↓↑		7	r ←	rVi3~i0

		r, q	1	0	1	0	1	1	0	1	r1	r0 q1 q0				↓↑		7	r ←	rVq

	XOR	r, i	1	1	0	1	0	0	r1	r0	i3	i2	i1	i0		↓↑		7	r ←	r∀		i3~i0

		r, q	1	0	1	0	1	1	1	0	r1	r0 q1 q0				↓↑		7	r ←	r∀ q

	CP	r, i	1	1	0	1	1	1	r1	r0	i3	i2	i1	i0		↓↑	↓↑	7	r-i3~i0

		r, q	1	1	1	1	0	0	0	0	r1	r0 q1 q0				↓↑	↓↑	7	r-q

	FAN	r, i	1	1	0	1	1	0	r1	r0	i3	i2	i1	i0		↓↑		7	rΛ i3~i0

		r, q	1	1	1	1	0	0	0	1	r1 r0 q1 q0					↓↑		7	rΛ q

	RLC	r	1	0	1	0	1	1	1	1	r1	r0	r1	r0		↓↑	↓↑	7	d3 ←			d2, d2 ←		d1, d1 ←		d0, d0 ←	C, C ←	d3

	RRC	r	1	1	1	0	1	0	0	0	1	1	r1	r0		↓↑	↓↑	5	d3 ←			C, d2 ←		d3, d1 ← d2, d0 ←			d1, C ←	d0

	INC	Mn	1	1	1	1	0	1	1	0	n3 n2 n1 n0					↓↑	↓↑	7	M(n3~n0) ←					M(n3~n0)+1

	DEC	Mn	1	1	1	1	0	1	1	1	n3 n2 n1 n0					↓↑	↓↑	7	M(n3~n0) ←					M(n3~n0)-1

	ACPX	MX, r	1	1	1	1	0	0	1	0	1	0	r1	r0		★ ↓↑	↓↑	7	M(X) ←				M(X)+r+C, X ←			X+1

	ACPY	MY, r	1	1	1	1	0	0	1	0	1	1	r1	r0		★ ↓↑	↓↑	7	M(Y) ←				M(Y)+r+C, Y ←			Y+1

	SCPX	MX, r	1	1	1	1	0	0	1	1	1	0	r1	r0		★ ↓↑	↓↑	7	M(X) ←				M(X)-r-C, X ←			X+1

	SCPY	MY, r	1	1	1	1	0	0	1	1	1	1	r1	r0		★ ↓↑	↓↑	7	M(Y) ←				M(Y)-r-C, Y ←			Y+1

	NOT	r	1	1	0	1	0	0	r1 r0		1	1	1	1		↓↑		7	r ←
	NOT	r	1	1	0	1	0	0	r1 r0		1	1	1	1		↓↑		7	r ←	r

S1C6200/6200A CORE CPU MANUAL

EPSON

19

Contents

Page © SEIKO EPSON CORPORATION 2001 All rights reserved SEIKO EPSON CORPORATION Devices Development tools S1C60 Family processors S1C62 Family processors Development tools for the S1C60/62 Family Page CONTENTS 1 DESCRIPTION 2 MEMORY AND OPERATIONS 3 INSTRUCTION SET A. S1C6200A (ADVANCED S1C6200) CORE CPU Page 1.1 System Features 1.2 Instruction Set Features 1.3 Differences between S1C6200 and S1C6200A Data Memory S1C6200 CORE CPU Program Memory Fig. 1.1 Block diagram 2.1 Program Memory (ROM) 2.1.1 Program counter block 2.1.2 Flags 2.1.3 Jump instructions 2.1.4 PSET with jump instructions 2.1.5 Call instructions 2.1.6 PSET instruction 2.1.7 CALZ instruction 2.1.8 RET and RETS instructions 2.1.9 Stack considerations for call instructions 2.2 Data Memory (within page) only (page specification) 4-bitdata • Index register IY •Stack pointer SP •Register pointer RP 2.3 ALU (Arithmetic Logic Unit) and Registers 2.3.1 D (decimal) flag and decimal operations 2.3.2 A and B registers 2.4 Timing Generator 2.4.1 HALT and SLP (sleep) modes 2.5 Interrupts 2.5.1 Interrupt vectors 2.5.2 I (interrupt) flag 2.5.3 Operation during interrupt generation S1C6200/6200A System clock CPU clock Fig. 2.5.3.2 Interrupt timing in the HALT mode Fig. 2.5.3.3 Interrupt timing in SLEEP mode Fig. 2.5.3.4 Interrupt timing with PSET 2.5.4 Initial reset 3.1 Instruction Indices a.Index by function b.Index in alphabetical order c.Index by operation code 3.1.1 By function Page Page 3.1.2 In alphabetical order Page Page 3.1.3 By operation code Page Page 3.2 Operands Flags 1.Carry flag 2.Zero flag 3.Decimal flag 3.4 Instruction Types (II) (III) (IV) (VI) ACPX MX,r ACPY MY,r Add with carry r-registerto M(Y), increment Y by ACPY MY,r ADC r,i Add with carry immediate data i to r-register ADC r,q Add with carry q-registerto r-register ADC r,q ADC XH,i Add with carry immediate data i to XH ADC XH,i ADC XL,i Add with carry immediate data i to XL ADC XL,i ADC YH,i Add with carry immediate data i to YH ADC YH,i ADC YL,i Add with carry immediate data i to YL ADC YL,i ADD r,i Add immediate data i to r-register ADD r,q Add q-registerto r-register AND r,i Logical AND immediate data i with r-register AND r,q Logical AND q-registerwith r-register CALL s Call subroutine CALZ s Call subroutine at page zero CP r,i Compare immediate data i with r-register CP r,q Compare q-registerwith r-register CP XH,i Compare immediate data i with XH CP XL,i Compare immediate data i with XL CP YH,i Compare immediate data i with YH CP YL,i Compare immediate data i with YL DEC Mn Decrement memory DEC SP Decrement stack pointer Disable interrupts Enable interrupts FAN r,i Logical AND immediate data i with r-registerfor flag check FAN r,q Logical AND q-registerwith r-registerfor flag check HALT INC Mn Increment memory by INC SP Increment stack pointer by INC Increment X-registerby INC Y Increment Y-registerby JPBA Indirect jump using registers A and B JP C,s Jump if carry flag is set JP NC,s Jump if not carry JP NZ,s Jump if not zero JP s Jump JP Z,s Jump if zero LBPX MX,e Load immediate data e to memory, and increment X by LD A,Mn Load memory into A-register LD B,Mn Load memory into B-register LD Mn,A Load A-registerinto memory LD Mn,B Load B-registerinto memory LDPX MX,i Load immediate data i into MX, increment X by LDPX MX,i LDPX r,q Load q-registerinto r-register,increment X by LDPY MY,i Load immediate data i into MY, increment Y by LDPY MY,i LDPY r,q Load q-registerinto r-register,increment Y by LDPY r,q LD r,i Load immediate data i into r-register LD r,q Load q-registerinto r-register LD r,SPH Load SPH into r-register LD r,SPL Load SPL into r-register LD r,XH Load XH into r-register LD r,XL Load XL into r-register LD r,XP Load XP into r-register LD r,YH Load YH into r-register LD r,YL Load YL into r-register LD r,YP Load YP into r-register LD SPH,r Load r-registerinto SPH LD SPH,r LD SPL,r Load r-registerinto SPL LD X,e Load immediate data e into X-register LD XH,r Load r-registerinto XH LD XL,r Load r-registerinto XL LD XP,r Load r-registerinto XP LD Y,e Load immediate data e into Y-register LD YH,r Load r-registerinto YH LD YL,r Load r-registerinto YL LD YP,r Load r-registerinto YP NOP5 No operation for 5 clock cycles NOP7 No operation for 7 clock cycles NOT r NOT r-register(one's complement) OR r,i Logical OR immediate data i with r-register OR r,q Logical OR q-registerwith r-register POP F Pop stack data into flags POP r Pop stack data into r-register POP XH Pop stack data into XH POP XL Pop stack data into XL POP XP Pop stack data into XP POP YH Pop stack data into YH POP YL Pop stack data into YL POP YP Pop stack data into YP PSET p Page set PUSH F Push flag onto stack PUSH r Push r-registeronto stack PUSH XH Push XH onto stack PUSH XL Push XL onto stack PUSH XP Push XP onto stack PUSH YH Push YH onto stack PUSH YL Push YL onto stack PUSH YP Push YP onto stack RCF Reset carry flag RDF Reset decimal flag RET RETD e RETS Return then skip an instruction RLC r Rotate r-registerleft with carry RRC r Rotate r-registerright with carry RST F,i Reset flags using immediate data RZF Reset zero flag SBC r,i Subtract with carry immediate data i from r-register SBC r,q Subtract with carry q-registerfrom r-register SCF Set carry flag SCPX MX,r Subtract with carry r-registerfrom M(X) and increment X by SCPX MX,r SCPY MY,r Subtract with carry r-registerfrom M(Y) and increment Y by SCPY MY,r SDF Set decimal flag SET F,i Set flags using immediate data SLP Sleep SUB r,q Subtract q-registerfrom r-register SZF Set zero flag XOR r,i Exclusive-ORimmediate data i with r-register XOR r,q Exclusive-OR q-registerwith r-register ABBREVIATIONS A1 Outline of Differences A2 Detailed Description of the Differences A2.1 Initial reset A2.2 Interrupt Operation during interrupt issuance a) During instruction execution b) At HALT mode <Reference 1> Writing on the interrupt mask register during EI <Reference 2> Reading the interrupt factor flag during EI APPENDIX B. INSTRUCTION INDEX ACPX MX,r ACPY MY,r ADC r,i ADC r,q LBPX MX,e LD A,Mn LD B,Mn LD Mn,A LD Mn,B PUSH r PUSH XH PUSH XL PUSH XP PUSH YH International Sales Operations In pursuit of “Saving” Technology, Epson electronic devices “Saving” Technology Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams Epson IS energy savings Core CPU Manual