Epson S1C6200A, S1C6200 b) At HALT mode, a) During instruction execution

APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU

Clock
Status
Instruction
	5-clock Instrruction			12-clock Instrruction				INT1 (*1)	INT2 (*1)	JP (*2)
					Interrupt
				Interrupt processing:		12-clock instruction		... 12.5 to 24.5 clock cycles
						7-clock instruction		... 12.5 to 19.5 clock cycles
						5-clock instruction		... 12.5 to 17.5 clock cycles
Status:		Fetch	Execute		Note:	(*1)	INT1 and INT2 are dummy instructions
						(*2)	Branches to the top of the interrupt service routine

a) During instruction execution

System clock
CPU clock
Status
Instruction	5-clock Instrruction			HALT					INT1 (*1)	INT2 (*1)	JP (*2)
								Interrupt
							Interrupt processing: 14 to 15 clock cycles
Status:		Fetch	Execute		Note:	(*1)		INT1 and INT2 are dummy instructions
						(*2)		Branches to the top of the interrupt service routine

b) At HALT mode

Clock

Status

Instruction

PSET

CALL

INT1 (*1)

INT2 (*1)

JP (*2)

Interrupt

Interrupt processing: PSET + CALL ... 12.5 to 24.5 clock cycles

PSET + JP ... 12.5 to 22.5 clock cycles

Status:

Fetch

Execute

Note:

(*1)

INT1 and INT2 are dummy instructions

(*2)

Branches to the top of the interrupt service routine

c)During "PSET" instruction execution Fig. A2.2.1 Timing chart of S1C6200A interrupt

S1C6200/6200A CORE CPU MANUAL EPSON 85