3 INSTRUCTION SET

LD SPH,r Load r-register into SPH

Source Format: LD SPH,rOperation: SPH r

OP-Code:

1

 

1

1

1

1

1

1

0

0

0

r1

r0

 

FE0H to FE3H

 

MSB

 

 

 

 

 

LSB

 

Type:

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock Cycles:

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Flag:

C – Not affected

 

 

 

 

 

 

 

 

 

Z – Not affected

 

 

 

 

 

 

 

 

 

D – Not affected

 

 

 

 

 

 

 

 

 

I

– Not affected

 

 

 

 

 

 

 

 

Description: Loads the contents of the r-register into the four high-order bits of the stack pointer.

Example:

 

LD SPH,A

 

 

LD SPH,MY

 

SPH

1001

 

0011

 

1100

 

A register

0011

 

0011

 

0011

 

Memory (MY)

1100

 

1100

 

1100

LD SPL,r

Load r-register into SPL

Source Format:

LD SPL,r

Operation:

SPL

r

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OP-Code:

1

1

1

1

1

1

1

1

0

0

r1

r0

FF0H to FF3H

 

MSB

 

 

 

 

 

 

 

 

 

LSB

Type: V

Clock Cycles: 5

Flag: C – Not affected

Z– Not affected D – Not affected I – Not affected

Description: Loads the contents of the r-register into the four low-order bits of the stack pointer.

Example:

 

LD SPL,B

 

 

LD SPL,MX

 

SPL

1011

 

0111

 

1111

 

B register

0111

 

0111

 

0111

 

Memory (MX)

1111

 

1111

 

1111

56

EPSON

S1C6200/6200A CORE CPU MANUAL