Finisar AN-2030 F i n i s a r, Current Address Read, Random Read, Sequential Address Read

AN-2030: Digital Diagnostic Monitoring Interface for Optical Transceivers F i n i s a r

Acknowledge Polling: Once the internally-timed write has started and the DDTC inputs are disabled, acknowledge polling can be initiated. The process involves transmitting a start condition followed by the device address. The R/W bit signifies the type of operation that is desired. The read or write sequence will only be allowed to proceed if the internal write cycle has completed and the DDTC responds with a zero.

Read Operations: After receiving a matching address byte with the R/W bit set high, the

device goes into the read mode of operation. There are three read operations: current address read, random read and sequential address read, described as follows:

Current Address Read

The DDTC has an internal address register that contains the address used during the last read or write operation, incremented by one. This data is maintained as long as Vcc is valid. If the most recent address was the last byte in memory, then the register resets to the first address. This address stays va lid between operations as long as power is available.

Once the device address is clocked in and acknowledged by the DDTC with the R/W bit set to high, the current address data word is clocked out. The master does not respond with a zero, but does generate a stop condition afterwards.

Random Read

A random read requires a dummy byte write sequence to load in the data word address. Once the device and data address bytes are clocked in by the master, and acknowledged by the DDTC, the master must generate another start condition. The master now initiates a current address read by sending the device address with the read/write bit set high. The DDTC will acknowledge the device address and serially clocks out the data byte.

Sequential Address Read

Sequential reads are initiated by either a current address read or a random address read. After the master receives the first data byte, the master responds with an Acknowledge Bit. As long as the DDTC receives this acknowledge after a byte is read, the maste r may clock out additional data words from the DDTC. After reaching address FFh, it resets to address 00h.

The sequential read operation is terminated when the master initiates a stop condition. The master does not respond with a zero.

9/26/02 Revision D Page 30